Multi-Mode Multi-Corner Clocktree Synthesis
AssigneeMentor Graphics Corporation
InventorsSivaprakasam Sunder, Kirk Schollman
Life of this patent
Estimating the term…
Abstract
A method for building a clock tree for an integrated circuit design. The clock tree has a plurality of clock tree nodes that couple to sink pins for circuit elements of the integrated circuit design to distribute the clock signal to the sink pins, which are clustered into one or more clusters. Timing information is determined to measure the clock signal delay from the root to the sink pins in the one or more clusters based on the placed one or more clock tree nodes. Different sets of timing information may be determined based on different sets of clock tree timing variation parameters.
Claims21
A method comprising:
- placing one or more clock tree nodes for a clock tree in a circuit design to distribute a clock signal to one or more sink pins in the circuit design;
- determining multiple sets of timing information for clock signal delay to the sink pins based on the placed one or more clock tree nodes, wherein each of the sets of timing information is based on a different set of clock tree timing variation parameters for the clock tree;
- using a computer to measure a plurality of clock skew values for one or more of the sink pins, wherein the clock skew values are measured for each of the sets of timing information;
- and
- optimizing the clock tree for the design based at least in part on the measured clock skew values for each of the sets of timing information.
One or more computer-readable media storing computer-readable instructions that, when executed by one or more processors cause the one or more processors to perform a method, the method comprising:
- placing one or more clock tree nodes for a clock tree in a circuit design to distribute a clock signal to one or more sink pins in the circuit design;
- determining multiple sets of timing information for the clock signal delay to the sink pins based on the placed one or more clock tree nodes, wherein each of the sets of timing information is based on a different set of clock tree timing variation parameters for the clock tree;
- measuring a plurality of clock skew values for the sink pins, wherein the clock skew values are measured for each of the sets of timing information;
- and
- adjusting the clock tree for the design based at least in part on the measured clock skew values for each of the sets of timing information.
An apparatus comprising:
- one or more processors;
- and
- one or more tangible media storing processor-readable instructions that, when executed by the one or more processors, cause the one or more processors to perform a method, the method comprising:
- placing one or more clock tree nodes for a clock tree in a circuit design to distribute a clock signal to one or more sink pins;
- determining multiple sets of timing information for the clock signal delay to the sink pins based on the placed one or more clock tree nodes, wherein each of the sets of timing information is based on a different set of clock tree timing variation parameters for the clock tree;
- measuring a plurality of clock skew values for the sink pins, wherein the clock skew values are measured for each of the sets of timing information;
- and
- adjusting the clock tree for the design based at least in part on the measured clock skew values for each of the sets of timing information.
Dependencies are inferred from the claim text.