# US 2012/0239989 A1 · Monitoring and Verifying a Clock State of a Chip

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- Number: US 2012/0239989 A1
- Document ID: US20120239989A1
- Status: Published application
- Kind: A1
- Application number: 13/046,865
- Filed: 2011-03-14
- Published: 2012-09-20
- Earliest claimed: 2011-03-14
- Assignees: International Business Machines Corporation
- Inventors: Daniel M. Crowell; David D. Sanner; Thi N. Tran
- Web page: https://patentgrep.com/patent/US20120239989A1

## CPC

- G06F 11/3055: {Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available (error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction of the data by redundancy in operations G06F11/14; error detection or correction by redundancy in hardware G06F11/16)}
- G06F 11/3024: {where the computing system component is a central processing unit [CPU]}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A mechanism is provided for monitoring and verifying a clock state of a chip that does not write out clock state information. Responsive to identifying an access to the chip, the access is scanned to identify a chip register and a clock domain that will be accessed. A determination is made as to whether a bit of a clock trust unit associated with the chip register and the clock domain indicates whether to trust a clock state associated with the bit in a logical clock state unit. Responsive to the bit of the clock trust unit indicating that the clock state associated with the bit in the logical clock state unit is trusted, the clock state from the logical clock state unit is identified. Responsive to the clock state matching the clock state required by the access, the access is forwarded to the chip for execution.

## Claims

### Claim 1

A method, in a data processing system, for monitoring and verifying a clock state of a chip that does not write out clock state information, the method comprising:
responsive to identifying an access to the chip, scanning, by the processor, the access to identify a chip register and a clock domain that will be accessed;
determining, by the processor, whether a bit of a clock trust unit associated with the chip register and the clock domain indicates whether to trust a clock state associated with the bit in a logical clock state unit;
responsive to the bit of the clock trust unit indicating that the clock state associated with the bit in the logical clock state unit is trusted, identifying, by the processor, the clock state from the logical clock state unit;
determining, by the processor, whether the clock state matches a clock state required by the access; and
responsive to the clock state matching the clock state required by the access, forwarding, by the processor, the access to the chip for execution.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
responsive to the bit of the clock trust unit indicating that the clock state associated with the bit in the logical clock state unit is un-trusted, reading, by the processor, a current clock state of the clock domain associated with the access from the chip;
updating, by the processor, the clock state in the logical clock state unit with the current clock state;
setting, by the processor, the bit in the clock trust unit to trusted;
determining, by the processor, whether the clock state matches a clock state required by the access; and
responsive to the clock state matching the clock state required by the access, forwarding, by the processor, the access to the chip for execution.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
responsive to the clock state failing to match the clock state required by the access, returning, by the processor, an invalid access error to a requestor of the access.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
responsive to the clock state failing to match the clock state required by the access, reading, by the processor, a current clock state of the clock domain associated with the access from the chip;
updating, by the processor, the clock state in the logical clock state unit with the current clock state;
setting, by the processor, the bit in the clock trust unit to trusted;
determining, by the processor, whether the clock state matches a clock state required by the access; and
responsive to the clock state matching the clock state required by the access, forwarding, by the processor, the access to the chip for execution.

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
responsive to the clock state failing to match the clock state required by the access, returning, by the processor, an invalid access error to a requestor of the access.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
determining, by the processor, whether the chip returns an access clock error indicating that the required clock state of the access does not match the clock state of the clock domain;
responsive to receiving the access clock error, reading, by the processor, a current clock state of the clock domain associated with the access from the chip;
updating, by the processor, the clock state in the logical clock state unit with the current clock state;
setting, by the processor, the bit in the clock trust unit to trusted;
determining, by the processor, whether the clock state matches a clock state required by the access; and
responsive to the clock state matching the clock state required by the access, forwarding, by the processor, the access to the chip for execution.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
responsive to the clock state failing to match the clock state required by the access, returning, by the processor, an invalid access error to a requestor of the access.

### Claim 8 (depends on 1)

The method of claim 1, wherein, upon initialization of the data processing system, the processor:
identifies all chips within hardware of the data processing system that do not write out clock state information;
for each identified chip, creates a logical clock state unit within cache of the data processing system, wherein the logical clock state unit comprises a bit for each clock domain within the chip and wherein each bit within the logical clock state unit holds an indication of the clock state of its respective clock domain of the chip;
for each logical clock state unit, creates a clock trust unit within the cache of the data processing system, wherein each clock trust unit comprises a bit for each bit within its associated logical clock state unit and wherein each bit within the clock trust unit holds an indication of the validity of the clock state in the associated bit of the logical clock state unit; and
initializes all of the bits in the clock trust units to un-trusted.

### Claim 9

A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to:
responsive to identifying an access to the chip, scan the access to identify a chip register and a clock domain that will be accessed;
determine whether a bit of a clock trust unit associated with the chip register and the clock domain indicates whether to trust a clock state associated with the bit in a logical clock state unit;
responsive to the bit of the clock trust unit indicating that the clock state associated with the bit in the logical clock state unit is trusted, identify the clock state from the logical clock state unit;
determine whether the clock state matches a clock state required by the access; and
responsive to the clock state matching the clock state required by the access, forward the access to the chip for execution.

### Claim 10 (depends on 9)

The computer program product of claim 9, wherein the computer readable program further causes the computing device to:
responsive to the bit of the clock trust unit indicating that the clock state associated with the bit in the logical clock state unit is un-trusted, read a current clock state of the clock domain associated with the access from the chip;
update the clock state in the logical clock state unit with the current clock state;
set the bit in the clock trust unit to trusted;
determine whether the clock state matches a clock state required by the access; and
responsive to the clock state matching the clock state required by the access, forward the access to the chip for execution.

### Claim 11 (depends on 10)

The computer program product of claim 10, wherein the computer readable program further causes the computing device to:
responsive to the clock state failing to match the clock state required by the access, return an invalid access error to a requestor of the access.

### Claim 12 (depends on 9)

The computer program product of claim 9, wherein the computer readable program further causes the computing device to:
responsive to the clock state failing to match the clock state required by the access, read a current clock state of the clock domain associated with the access from the chip;
update the clock state in the logical clock state unit with the current clock state;
set the bit in the clock trust unit to trusted;
determine whether the clock state matches a clock state required by the access;
responsive to the clock state matching the clock state required by the access, forward the access to the chip for execution; and
responsive to the clock state failing to match the clock state required by the access, return an invalid access error to a requestor of the access.

### Claim 13 (depends on 9)

The computer program product of claim 9, wherein the computer readable program further causes the computing device to:
determine whether the chip returns an access clock error indicating that the required clock state of the access does not match the clock state of the clock domain;
responsive to receiving the access clock error, read a current clock state of the clock domain associated with the access from the chip;
update the clock state in the logical clock state unit with the current clock state;
set the bit in the clock trust unit to trusted;
determine whether the clock state matches a clock state required by the access;
responsive to the clock state matching the clock state required by the access, forward the access to the chip for execution; and
responsive to the clock state failing to match the clock state required by the access, return an invalid access error to a requestor of the access.

### Claim 14 (depends on 9)

The computer program product of claim 9, wherein, upon initialization of the data processing system, the computer readable program further causes the computing device to:
identify all chips within hardware of the data processing system that do not write out clock state information;
for each identified chip, create a logical clock state unit within cache of the data processing system, wherein the logical clock state unit comprises a bit for each clock domain within the chip and wherein each bit within the logical clock state unit holds an indication of the clock state of its respective clock domain of the chip;
for each logical clock state unit, create a clock trust unit within the cache of the data processing system, wherein each clock trust unit comprises a bit for each bit within its associated logical clock state unit and wherein each bit within the clock trust unit holds an indication of the validity of the clock state in the associated bit of the logical clock state unit; and
initialize all of the bits in the clock trust units to un-trusted.

### Claim 15

An apparatus, comprising:
a processor; and
a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to:
responsive to identifying an access to the chip, scan the access to identify a chip register and a clock domain that will be accessed;
determine whether a bit of a clock trust unit associated with the chip register and the clock domain indicates whether to trust a clock state associated with the bit in a logical clock state unit;
responsive to the bit of the clock trust unit indicating that the clock state associated with the bit in the logical clock state unit is trusted, identify the clock state from the logical clock state unit;
determine whether the clock state matches a clock state required by the access; and
responsive to the clock state matching the clock state required by the access, forward the access to the chip for execution.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the instructions further cause the processor to:
responsive to the bit of the clock trust unit indicating that the clock state associated with the bit in the logical clock state unit is un-trusted, read a current clock state of the clock domain associated with the access from the chip;
update the clock state in the logical clock state unit with the current clock state;
set the bit in the clock trust unit to trusted;
determine whether the clock state matches a clock state required by the access; and
responsive to the clock state matching the clock state required by the access, forward the access to the chip for execution.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein the instructions further cause the processor to:
responsive to the clock state failing to match the clock state required by the access, return an invalid access error to a requestor of the access.

### Claim 18 (depends on 15)

The apparatus of claim 15, wherein the instructions further cause the processor to:
responsive to the clock state failing to match the clock state required by the access, read a current clock state of the clock domain associated with the access from the chip;
update the clock state in the logical clock state unit with the current clock state;
set the bit in the clock trust unit to trusted;
determine whether the clock state matches a clock state required by the access;
responsive to the clock state matching the clock state required by the access, forward the access to the chip for execution; and
responsive to the clock state failing to match the clock state required by the access, return an invalid access error to a requestor of the access.

### Claim 19 (depends on 15)

The apparatus of claim 15, wherein the instructions further cause the processor to:
determine whether the chip returns an access clock error indicating that the required clock state of the access does not match the clock state of the clock domain;
responsive to receiving the access clock error, read a current clock state of the clock domain associated with the access from the chip;
update the clock state in the logical clock state unit with the current clock state;
set the bit in the clock trust unit to trusted;
determine whether the clock state matches a clock state required by the access;
responsive to the clock state matching the clock state required by the access, forward the access to the chip for execution; and
responsive to the clock state failing to match the clock state required by the access, return an invalid access error to a requestor of the access.

### Claim 20 (depends on 15)

The apparatus of claim 15, wherein, upon initialization of the data processing system, the instructions further cause the processor to:
identify all chips within hardware of the data processing system that do not write out clock state information;
for each identified chip, create a logical clock state unit within cache of the data processing system, wherein the logical clock state unit comprises a bit for each clock domain within the chip and wherein each bit within the logical clock state unit holds an indication of the clock state of its respective clock domain of the chip;
for each logical clock state unit, create a clock trust unit within the cache of the data processing system, wherein each clock trust unit comprises a bit for each bit within its associated logical clock state unit and wherein each bit within the clock trust unit holds an indication of the validity of the clock state in the associated bit of the logical clock state unit; and
initialize all of the bits in the clock trust units to un-trusted.