Synchronous data processing system and method

A memory controller for use with a memory module of a synchronous data processing system, the memory controller comprising:

• a clock inverter for receiving an input clock signal and transmitting an inverted clock signal to the memory module, wherein the inverted clock signal incurs a first propagation delay prior to reaching the memory module as a memory clock signal;
• a clock signal distribution module that generates a feedback signal by routing the memory clock signal from the memory module to the memory controller such that the clock signals transferred between the memory controller and the memory module have substantially the same phase delay as that of data transmitted between the memory module and the memory controller.

In a synchronous data processing system, a method for transferring data between a memory module and a memory controller, comprising:

• receiving an input clock signal;
• transmitting an inverted input clock signal to the memory module to generate a memory clock signal for the memory module;
• feeding back the memory clock signal from the memory module to the memory controller such that the clock signals transferred between the memory controller and the memory module incur substantially the same phase delay as that of data transmitted between the memory module and the memory controller.