Method for compensating a timing signal, an integrated circuit and electronic device
AssigneeFreescale Semiconductor, Inc.
InventorsMichael Priel, Leonid Fleshel, Anton Rozen
Life of this patent
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Abstract
A method for compensating a timing signal with which an outputting of data states of at least one data signal is synchronised. The method comprises receiving a current set of data states and a next set of data states, identifying state transitions between the current set of data states and the next set of data states, determining an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.
Claims16
A method comprising:
- receiving a current set of data states and a next set of data states;
- identifying state transitions between the current set of data states and the next set of data states;
- determining an amount of compensation to apply to a timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, wherein the outputting of data states is synchronized with the timing signal;
- and
- applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.
An integrated circuit device comprising:
- a timing circuit arranged to generate a timing signal with which an outputting of data states of at least one data signal is synchronised, wherein the timing circuit comprises a compensation circuit arranged to:
- receive a current set of data states and a next set of data states,
- identify state transitions between the current set of data states and the next set of data states,
- determine an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and
- apply the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.
An electronic device comprising:
- a timing circuit arranged to generate a timing signal with which an outputting of data states of at least one data signal is synchronised, wherein the timing circuit comprises a compensation circuit arranged to:
- receive a current set of data states and a next set of data states,
- identify state transitions between the current set of data states and the next set of data states,
- determine an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and
- apply the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.
Dependencies are inferred from the claim text.