Independent Power Control of Processing Cores
AssigneeIntel Corporation
InventorsStephen Gunther, Edward A. Burton, Anant Deval, Stephen Jourdan, Robert Greiner, Michael Cornaby
Life of this patent
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Abstract
Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
Claims29
A processor comprising:
- a memory controller;
- two processing cores, wherein each of the two processing cores include at least a decoder and one or more out-of-order execution units;
- a level one (L1) and a level two (L2) cache;
- and
- a power control logic coupled to one or more voltage modification circuits and clock gating control circuits,
- wherein the one or more voltage modification circuits are to independently control a voltage of at least one or more portions of the processor based on a requirement of a load of the at least one or more portions, wherein the voltage best matches the requirement of the load of the at least one or more portions, and
- wherein the one or more clock gating control circuits are to cause one or more clocks to the at least one or more portions to be independently gated.
A method in a multi-core processor, comprises independently controlling a clock frequency and voltage supplied to a first portion of the processor based on the workload of the first portion of the processor and without detecting a power state of a second portion of the processor,
- wherein the multi-core processor includes a plurality of cores, wherein each of the plurality of cores include at least a decoder, a reorder buffer, an out-of-order execution unit, and a retirement unit and coupled to a cache memory including at least one of a level one (L1) and level two (L2) cache.
A machine-readable medium having stored thereon data representing an integrated circuit, which when fabricated by a machine, is to perform a method comprising:
- independently controlling a clock frequency and voltage supplied to at least one or more portions based on the workload of the at least one or more portions, wherein the integrated circuit includes a plurality of cores, wherein each of the plurality of cores include at least a decoder, a reorder buffer, an out-of-order execution unit, and a retirement unit and coupled to a cache memory including at least one of a level one (L1) and level two (L2) cache.
Dependencies are inferred from the claim text.