Dual thread processor

A system comprising:

• a memory to store instructions for a first processor thread, and to store instructions for a second processor thread;
• and
• a processor comprising a first pipeline stage, a second pipeline stage, a first selector configured to provide data to the first pipeline stage, a first input register configured to provide data to the first selector, a second input register configured to provide data to the first selector, a second selector configured to receive data output of the first pipeline stage, a first output register configured to receive the data output from the second selector and to provide the data output to the second pipeline stage, and a second output register configured to receive the data output from the second selector and to provide the data output to the second pipeline stage,
• wherein the processor further comprises a first thread allocation counter configured to store a first processor time allocation that controls first periods of processor time for the first processor thread, the first processor thread retaining control of the processor during each of the first periods of processor time, wherein the processor is configured to cause data associated with the first processor thread to pass through the first input register, the first pipeline stage, the first output register, and the second pipeline stage during the first periods of processor time,
• wherein the processor further comprises a second thread allocation counter configured to store a second processor time allocation that controls second periods of processor time for the second processor thread, the second processor thread retaining control of the processor during each of the second periods of processor time, wherein the processor is configured to cause data associated with the second processor thread to pass through the second input register, the first pipeline stage, the second output register, and the second pipeline stage during the second periods of processor time, and
• wherein the processor is configured to receive an input defining processor time to be allocated to the first processor thread, the second processor thread, or both, and to use the input to change the first, second, or both thread allocation counters such that subsequent periods of processor times for the first, second, or both processor threads are affected.

A method, comprising:

• loading values into two or more hardware allocation counters of a processor based on received input, wherein the values determine a weighting that corresponds to processor time allocated to two or more processor threads, which correspond to the two or more hardware allocation counters;
• retrieving and executing instructions of the two or more processor threads in a pipeline of the processor in accordance with two or more program counters, which correspond to the two or more processor threads, wherein the retrieving and executing is performed separately for respective ones of the two or more processor threads;
• and
• performing a context switch automatically, based on an output of at least one of the two or more hardware allocation counters, between the separate retrieving and executing of instructions of the two or more processor threads according to the allocated processor time.