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US 2012/0239907 A1Published application
Active memory command engine and method
AssigneeMicron Technology, Inc.
InventorGraham Kirsch
Life of this patent
Estimating the term…
Abstract
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored.
Claims20
An apparatus, comprising:
- a command engine configured to provide a microinstruction of a first type and a microinstruction of a second type;
- a first memory circuit coupled to the command engine and configured to receive the microinstruction of the first type from the command engine, the first memory circuit further configured to execute a command corresponding to the microinstruction of the first type on a first set of data;
- and
- a second memory circuit coupled to the command engine and configured to receive the microinstruction of the second type from the command engine, the second memory circuit further configured to execute a command corresponding to the microinstruction of the second type on a second set of data.
1 more element
An active memory, comprising:
- a command engine configured to provide a command of a first type and a command of a second type;
- a first control unit configured to receive the command of the first type and provide a routine responsive, at least in part, to receipt of the command of the second type;
- and
- a second control unit configured to receive the command of the second type and provide a memory command responsive, at least in part, to receipt of the command of the second type.
1 more element
A method, comprising:
- generating a microinstruction responsive, at least in part, to receipt of an instruction comprising one or more identification bits indicative of a type of the instruction, wherein the microinstruction is based, at least in part, on the one or more identification bits;
- generating a command responsive, at least in part, to receipt of the microinstruction;
- providing the command to a memory circuit;
- and
- executing the command on a set of data using the memory circuit.
2 more elements
Dependencies are inferred from the claim text.