Address transforming circuit and semiconductor memory device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsSeok-Il Kim, You-Keun Han, Sung-Ho Choi
Life of this patent
Estimating the term…
Abstract
An address transforming circuit that can change a memory mapping when a system is booted includes a switch control signal generating circuit and an address transforming unit. The switch control signal generating circuit generates alternately enabled switch control signals synchronized with a reset signal. The address transforming unit transforms bits of a first address to generate a second address in response to the switch control signals. Accordingly, a semiconductor memory device including the address transforming circuit has a long lifetime and high reliability.
Claims20
An address transforming circuit, comprising:
- a switch control signal generating circuit configured to generate alternately enabled switch control signals that are synchronized with a reset signal;
- and
- an address transforming unit configured to transform bits of a first address to generate a second address in response to the switch control signals.
A semiconductor memory device, comprising:
- a memory cell array;
- an address transforming circuit configured to generate alternately enabled switch control signals synchronized with a reset signal, and configured to transform bits of a first address to generate a transformed row address and a transformed column address in response to the switch control signals;
- a row decoder configured to decode the transformed row address and select a specified row of the memory cell array based on the decoded row address;
- and
- a column decoder configured to decode the transformed column address and select a specified column of the memory cell array based on the decoded column address.
An address transforming circuit, comprising:
- a switch control signal generating circuit configured to generate switch control signals in response to a reset signal and an address mapping counter value;
- and
- an address transforming unit configured to transform bits of a first address to generate a second address in response to the switch control signals.
Dependencies are inferred from the claim text.