Memory system with independently adjustable core and interface data rates

A method of operation in an integrated circuit, the method comprising:

• receiving a memory access command;
• transferring in parallel a first number of data bits between core circuitry and interface circuitry in response to the received command;
• and
• transferring in parallel a second number of data bits between the interface circuitry and a set of data pins, wherein the ratio of the first number to the second number is a non-power-of-2 value.

A memory system comprising:

• an integrated circuit memory device having a memory core, and a number of core signal paths for accessing data stored in the memory core;
• an integrated circuit memory controller having a logic core;
• and
• a number of data links connecting the integrated circuit memory device to the integrated circuit memory controller, wherein the ratio of the number of core signal paths to the number of data links comprises a non-power-of-2 value.

A clock circuit comprising:

• a bit-rate clock input to receive a bit rate clock signal at a bit rate frequency;
• a state machine coupled responsive to the bit rate clock, the state machine including
• a counter responsive to the bit rate clock to generate a plurality of state signals, and
• a state decoder coupled to the counter to generate actions based on predetermined subsets of the plurality of states, wherein a first clock signal at a first frequency is generated in response to a first subset of the plurality of state signals, and a second clock signal at a second frequency is generated in response to a second subset of the plurality of state signals.