Resource sharing to reduce implementation costs in a multicore processor

A method, comprising:

• concurrently accessing multiple ones of a plurality of cache banks, wherein the multiple cache banks correspond to respective ones of a plurality of controllers that are included within a given one of a plurality of tag units of a hardware lower-level cache, wherein the lower-level cache is coupled via an interconnect network to a plurality of hardware processor cores, each comprising a respective higher-level cache;
• and
• generating multiple concurrent requests to access a resource shared by the controller included within the given tag unit, wherein the resource includes one or more of:
• an interconnect egress port coupled to the interconnect network, an interconnect ingress port coupled to the interconnect network, a test controller, or a data storage structure.

A system, comprising:

• a system memory;
• and
• a processor coupled to the system memory, wherein the processor comprises:
• a plurality of hardware processor cores, each comprising a respective higher-level cache;
• a hardware lower-level cache comprising a plurality of tag units each comprising a plurality of controllers, wherein each controller corresponds to a respective one of a plurality of cache banks configured to store data, and wherein the controllers are concurrently operable to access their respective cache banks;
• and
• an interconnect network configured to convey data between the processor cores and the lower-level cache;
• wherein the controllers included in a given one of the tag units are configured to share access to a resource that includes one or more of:
• an interconnect egress port coupled to the interconnect network, an interconnect ingress port coupled to the interconnect network, a test controller, or a data storage structure.