Memory access system and method for optimizing SDRAM bandwidth

A memory access method for optimizing synchronous dynamic random access memory (SDRAM) bandwidth, which is applied on a system on a chip (SoC) for executing SDRAM commands in a manner of optimized bandwidth, the method comprising the steps of

• (A) using a memory bus arbiter and data switch circuit to select or grant a next memory access command;
• (B) using the memory bus arbiter and data switch circuit to send the next memory access command to a memory access system for optimizing the SDRAM bandwidth;
• (C) using the memory access system to decode the next memory access command into SDRAM commands;
• (D) determining whether the memory access command is generated by a specific bus master;
• (E) storing the SDRAM commands in an alternative SDRAM command queue when it is determined in step (D) that the memory access command is generated by the specific bus master, and executing step (G);
• (F) storing the SDRAM commands in a general SDRAM command queue when it is determined in step (D) that the memory access command is not generated by the specific bus master, and executing step (G);
• and
• (G) extracting the SDRAM commands with a minimum penalty from the general SDRAM command queue or the alternative SDRAM command queue, and storing the SDRAM command with the minimum penalty in a minimum penalty SDRAM command queue.