Fifo apparatus for the boundary of clock trees and method thereof

A method of first in and first out (FIFO), utilizing a first clock signal of a first clock domain to receive an input signal, and utilizing a second clock signal of a second clock domain to output an output signal, the method comprises the following steps:

• utilizing at least three write registers to receive the input signal according to the first clock signal, wherein each write register has a first input;
• enabling the at least three write registers in accordance with a sequence and generating an initial signal according to the first clock signal;
• and
• utilizing the initial signal to output the first signals as the output signal in accordance with the sequence according to the second clock signal;
• wherein the second clock domain is based on a clock tree generated according to the first clock domain.

A first in and first out (FIFO) apparatus, utilizing a first clock signal of a first clock domain to receive an input signal, and utilizing a second clock signal of a second clock domain to output an output signal, wherein the apparatus comprises:

• a random access memory (SRAM), in the first clock domain, having at least three address for receiving the input signal;
• and
• a first controller, in the first clock domain, for generating an initial signal, and write the input signal to the at least three address in accordance with a sequence;
• and
• a second controller, in the second clock domain, for receiving the initial signal through an asynchronous interface and controlling the SRAM output the input signal as the output signal from the at least three address in accordance with the sequence according to the initial signal;
• wherein the second clock domain is based on a clock tree generated from the first clock domain.