Solid-state storage device with multi-level addressing

A method for mapping a plurality of logical addresses received from a host to a plurality of physical addresses in a flash memory device, the method comprising:

• determining in a controller a first parameter, a second parameter, and a third parameter from a logical address;
• mapping the first parameter of the logical address to a first address in a first table stored in a volatile memory;
• reading a second table from a flash memory device based on the first address;
• mapping the second parameter of the logical address to a second address in the second table;
• reading a third table from the flash memory device based on the second address;
• and
• mapping the third parameter of the logical address to a third address in the third table, wherein the third address is a physical address in the flash memory device containing data associated with the logical address.

A processor-readable medium containing executable instructions for mapping a plurality of logical addresses received from a host to a plurality of physical addresses in a flash memory device, the executable instructions comprising code for:

• determining a first parameter, a second parameter, and a third parameter from a logical address;
• mapping the first parameter of the logical address to a first address in a first table stored in a volatile memory;
• reading a second table from a flash memory device based on the first address;
• mapping the second parameter of the logical address to a second address in the second table;
• reading a third table from the flash memory device based on the second address;
• and
• mapping the third parameter of the logical address to a third address in the third table, wherein the third address is a physical address in the flash memory device containing data associated with the logical address.