Solid state device with allocated flash cache
AssigneeSTEC, Inc.
InventorMark Moshayedi
Life of this patent
Estimating the term…
Abstract
A flash storage device, and methods for a flash storage device, having improved write performance are provided. Data is received from a host system, the data comprising a data segment, the data segment is temporarily stored in a data buffer of the random access memory, the data segment is assigned to a logical block address, and the data segment is written to an allocated cache portion of the flash memory. Subsequently, the data segment is written from the allocated cache portion of the flash memory to a main storage portion of the flash memory.
Claims49
A method of transferring data in a flash storage device comprising a random access memory and a flash memory, the method comprising:
- receiving data from a host system, the data comprising a data segment;
- temporarily storing the data segment in a data buffer of the random access memory;
- assigning the data segment to a logical block address;
- determining if the data segment stored in the data buffer comprises sequential data or random data;
- and
- writing the data segment to an allocated cache portion of the flash memory if the data segment is determined to comprise random data.
(canceled)
A flash storage device comprising:
- a flash memory;
- a random access memory;
- and
- a controller configured to perform the steps of:
- receiving data from a host system, the data comprising a data segment;
- temporarily storing the data segment in a data buffer of the random access memory;
- assigning the data segment to a logical block address;
- determining if the data segment stored in the data buffer comprises sequential data or random data;
- and
- writing the data segment to an allocated cache portion of the flash memory if the data segment is determined to comprise random data.
(canceled)
A non-transitory machine readable medium carrying one or more sequences of instructions for managing memory operations in a flash storage device having a flash memory, a random access memory and a controller, wherein execution of the one or more sequences of instructions by one or more processors in the controller cause the one or more processors to perform the steps of:
- receiving data from a host system, the data comprising a data segment;
- temporarily storing the data segment in a data buffer of the random access memory;
- assigning the data segment to a logical block address;
- determining if the data segment stored in the data buffer comprises sequential data or random data;
- and
- writing the data segment to an allocated cache portion of the flash memory if the data segment is determined to comprise random data.
Dependencies are inferred from the claim text.