High speed input/output performance in solid state devices
AssigneeSTEC, Inc.
InventorsWilliam CALVERT, Stephen Russell Boorman, Simon Mark Haynes
Life of this patent
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Abstract
A method of transferring data in a flash storage device comprising a random access memory and a plurality of channels of a flash array is provided. The method comprises receiving a plurality of data segments from a host system, storing the plurality of data segments in the random access memory, allocating the plurality of data segments among the plurality of channels of the flash array, and writing the allocated data segments from the random access memory to the respective channels of the flash array.
Claims18
A method of storing data in a flash storage device, the method comprising:
- receiving a plurality of data sectors from a host system, wherein each of the data sectors is associated with a host logical address;
- storing a plurality of data segments in the random access memory, wherein each data segment comprises one of the plurality of data sectors from the host system;
- mapping the host logical address of each of the plurality of data sectors to a flash logical address of a corresponding data segment;
- allocating the plurality of data segments among a plurality of channels of a flash array based on the flash logical addresses of the respective data segments;
- and
- writing the allocated data segments from the random access memory to the respective channels of the flash array.
A flash storage device comprising:
- a random access memory;
- a flash array comprising a plurality of flash memories and a respective plurality of channels;
- and
- a controller configured to receive a plurality of data sectors from a host system, wherein each of the data sectors is associated with a host logical address, to store a plurality of data segments in the random access memory, wherein each data segment comprises one of the plurality of data sectors from the host system, to map the host logical address of each of the plurality of data sectors to a flash logical address of a corresponding data segment, to allocate the plurality of data segments among the plurality of channels of the flash array based on the flash logical addresses of the respective data segments, and to write the allocated data segments from the random access memory to the respective channels of the flash array.
Dependencies are inferred from the claim text.