Mitigation of embedded controller starvation in real-time shared spi flash architecture

A method, comprising:

• in an embedded controller, receiving and transmitting memory transactions from and to a Central Processing Unit (CPU) chipset over a first bus interface that does not support bus arbitration, and communicating with a memory and transferring the memory transactions of the CPU chipset to and from the memory over a second bus interface;
• evaluating a starvation condition that identifies an inability of the embedded controller to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces;
• and
• invoking a predefined corrective action when the starvation condition is met.

A computer, comprising:

• a Central Processing Unit (CPU) chipset;
• a memory;
• and
• an embedded controller, comprising:
• a microcontroller core;
• a first bus interface, which is configured to receive and transmit memory transactions from and to the CPU chipset and does not support bus arbitration;
• a second bus interface, which is configured to communicate with the memory and to transfer the memory transactions of the CPU chipset to and from the memory;
• and
• memory control circuitry, which is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.