Multi-core microprocessor internal bypass bus

A microprocessor, comprising:

• a die having at least two cores and at least two sets of physical input/output landing pads, pairs of corresponding ones of said sets of landing pads coupling the microprocessor to a bidirectional processor bus coupled to a chipset;
• bus interfaces coupling respective inputs and outputs of each core to corresponding physical input/output landing pads of the die;
• and
• a bypass bus on the die that enables at least first and second complementary sets of die cores to bypass the processor bus in order to communicate directly with each other, the bypass bus providing bus lines corresponding to processor bus lines;
• wherein the bypass bus does not carry signals off the die, drive signals on the processor bus to the chipset, or receive chipset-drive signals from the processor bus.

A method of inter-core communication among cores of a multi-core die, the method comprising:

• receiving, on a bus interface of a core, both signals from a processor bus connecting the multi-core die to a chipset and signals from a corresponding bypass bus connecting the core to a complementary, bypass-bus-connected core of the multi-core die, wherein the bypass bus does not carry signals off the die, drive signals on the processor bus to the chipset, or receive chipset-drive signals from the processor bus;
• detecting whether the processor bus is being driven by the chipset or the complementary core;
• and
• if the processor bus is being driven by the complementary core, causing the bus interface to select signals from the bypass bus instead of signals from the processor bus to drive corresponding core inputs.

A method of inter-core communication among cores of a multi-core die, the method comprising:

• receiving, on a bus interface shared by a set of twin cores of the die, both signals from a processor bus connecting the multi-core die to a chipset and signals from a corresponding bypass bus connecting the set of twin cores to a complementary, bypass-bus-connected set of twin cores of the multi-core die, wherein the bypass bus does not carry signals off the die, drive signals on the processor bus to the chipset, or receive chipset-drive signals from the processor bus;
• detecting whether the processor bus is being driven by the chipset or a core of the complementary set of twin cores;
• and
• if the processor bus is being driven by a core of the complementary set of twin cores, causing the bus interface to select signals from the bypass bus instead of signals from the processor bus to drive corresponding core inputs.