US 2012/0239719 A1 · Floating-Point Addition Acceleration

Abstract

Embodiments of the present invention generate a normalized floating-point sum from at least two floating-point addends. The mantissa of an un-normalized floating-point sum is generated. A pointer is generated which indicates the location of the left-most significant digit (LSD) in the mantissa of the un-normalized floating-point sum. A plurality of possible values for the exponent of the normalized floating-point sum are generated, in parallel with each other and in parallel with the mantissa addition, based on a common exponent value (e.g., the largest of the two addends' exponent values). Based on the LSD pointer, one of the possible values is selected as the exponent of the normalized floating-point sum. The mantissa of the un-normalized floating-point sum is normalized to yield the mantissa of the normalized floating-point sum. By generating the possible exponent values in parallel, embodiments of the present invention can result in significant time savings over prior-art methods.

Claims20

Dependent claims

A machine-implemented method for generating a normalized floating-point sum from at least first and second floating-point addends, wherein each addend comprises a mantissa and an exponent, and the normalized floating-point sum comprises a mantissa and an exponent, the method comprising:

(a) a mantissa generator generating the mantissa of the normalized floating-point sum based on the first and second floating-point addends;
(b) an exponent generator generating a plurality of possible values for the exponent of the normalized floating-point sum based on a common exponent value;
and
(c) an exponent selector selecting one of the possible values to generate the exponent of the normalized floating-point sum.

1 more element

Dependencies are inferred from the claim text.

Floating-Point Addition Acceleration

Life of this patent

Floating-Point Addition Acceleration

Life of this patent

Abstract

Claims20