Consistent Hierarchical Timing Model with Crosstalk Consideration
AssigneeSynopsys, Inc.
InventorsPeivand Tehrani, Li Ding, Narender Hanchate, Rupesh Nayak, Yazdan Aghaghiri
Life of this patent
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Abstract
A method and apparatus to provide a hierarchical timing model with crosstalk consideration is provided. In one embodiment, the method comprises performing block level analysis of a circuit, in one or a plurality of iterations, and storing per iteration data. The method further comprises, in one embodiment, utilizing the per iteration data in performing top level analysis of the circuit.
Claims23
A method for hierarchical static timing analysis comprising:
- performing one or more iterations in static timing analysis on a lower-level block, the lower level block;
- storing intermediate data of the static timing analysis of the lower-level block for an iteration, including simplified representations of aggressor effects, the simplification based on an plurality aggressor types;
- and
- loading and utilizing the stored intermediate data in performing static timing analysis on an upper-level block.
A method for hierarchical static timing analysis comprising:
- performing one or more iterations in static timing analysis on a lower-level block;
- storing intermediate data of the static timing analysis of the lower-level block for an iteration;
- loading and utilizing the stored intermediate data in performing static timing analysis on an upper-level block.
A method of marking and modeling aggressors in a circuit, the method comprising:
- evaluating a victim net impacted by one or more aggressors;
- classifying the one or more aggressors into types;
- simplifying aggressor representation based on the determined type.
A system to enable hierarchical static timing analysis, comprising a computer system including a processor, memory and hard disk, the system comprising:
- the processor to perform iterative static timing analysis on a lower-level block;
- a data storage device to store intermediate data of the static timing analysis of the lower-level block for each iteration;
- a volatile memory to store a retrieved intermediate data from the analysis of the lower-level block on a per iteration basis;
- and
- the processor to utilize the intermediate data of the iteration in the volatile memory to perform static timing analysis on an upper-level block.
An article of manufacture comprising a machine-accessible non-transitory medium including data that, when accessed by a machine, cause the machine to perform operations comprising:
- performing one or more iterations in static timing analysis on a lower-level block, the lower level block;
- storing intermediate data of the static timing analysis of the lower-level block for an iteration, including simplified representations of aggressor effects, the simplification based on an plurality aggressor types;
- and
- loading and utilizing the stored intermediate data in performing static timing analysis on an upper-level block.
Dependencies are inferred from the claim text.