Semiconductor integrated circuit, test method and information processing apparatus

A method of testing a semiconductor integrated circuit performed by a testing device, the semiconductor integrated circuit including a semiconductor integrated circuit including a plurality of shift registers to which test patterns are supplied;

• a pseudorandom number generator configured to generate, based on the test patterns supplied to the shift registers, pseudorandom numbers utilized as masking information corresponding to output responses of the shift registers;
• a masking information inverter configured to invert, on receiving a first control signal, the masking information corresponding to the output responses of the shift registers indicated by the first control signal;
• and an initial value storage configured to store initial values of the pseudorandom numbers, the pseudorandom numbers generated by the pseudorandom number generator being, on receiving a second control signal, initialized with the initial values of the pseudorandom numbers stored in the initial value storage, the method comprising:
• supplying the first control signal to the semiconductor integrated circuit based on test data generated in advance;
• and
• supplying the second control signal to initialize the pseudorandom numbers for the corresponding test patterns.

A non-transitory computer-readable medium storing a program, which, when processed by a processor, causes a computer to execute a searching process, the searching process comprising:

• searching for initial values of pseudorandom numbers, which are capable of masking output responses corresponding to unknown values output by a part of flip-flops or all of the flip-flops contained in a corresponding one of shift registers included in a semiconductor integrated circuit, wherein
• the semiconductor integrated circuit includes:
• the shift registers to which test patterns are supplied;
• a pseudorandom number generator configured to generate, based on the test patterns supplied to the shift registers, the pseudorandom numbers utilized as masking information corresponding to the output responses of the shift registers;
• a masking information inverter configured to invert, on receiving a first control signal, the masking information corresponding to the output responses of the shift registers indicated by the first control signal;
• and
• an initial value storage configured to store the initial values of the pseudorandom numbers, wherein the pseudorandom numbers generated by the pseudorandom number generator are, on receiving a second control signal, initialized with the initial values of the pseudorandom numbers stored in the initial value storage.