Radio communication device, transmission circuit and buffer circuit
AssigneeKabushiki Kaisha Toshiba
InventorJun Deguchi
Life of this patent
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Abstract
According to one embodiment, a buffer circuit has a capacitor comprising a first terminal and a second terminal, an input signal being inputted to the first terminal, a first inverting amplifier circuit configured to invert and amplify a signal of the second terminal of the capacitor, a second inverting amplifier circuit configure to invert and amplify an output signal of the first inverting amplifier circuit, and a MOS (Metal Oxide Semiconductor) transistor comprising a third terminal, a fourth terminal and a gate, the third terminal being connected to the second terminal of the capacitor, the fourth terminal being connected to a connection node of the first and the second inverting amplifier circuits, an inversion signal of the input signal being inputted to the gate.
Claims8
A radio communication device comprising at least one of a signal transmitter and a signal receiver,
- wherein the signal transmitter comprises:
- a signal transmission circuit configured to modulate an input radio signal inputted from an outside based on a first oscillation signal, and to transmit the modulated input radio signal from an antenna;
- and
- a first transmission circuit configured to transmit the first oscillation signal to the signal transmission circuit, and
- the signal receiver comprises:
- a signal reception circuit configured to demodulate a reception signal received at the antenna based on the first oscillation signal or based on a second oscillation signal different from the first oscillation signal, and to output the demodulated reception signal to an outside;
- and
- a second transmission circuit configured to transmit the first or second oscillation signal to the signal reception circuit,
- wherein each of the first and the second transmission circuits comprises a plurality of buffer circuits connected in series,
- wherein each of the buffer circuits comprises:
- a capacitor comprising a first terminal and a second terminal, an input signal being inputted to the first terminal;
- a first inverting amplifier circuit configured to invert and amplify a signal of the second terminal of the capacitor;
- a second inverting amplifier circuit configure to invert and amplify an output signal of the first inverting amplifier circuit;
- and
- a MOS (Metal Oxide Semiconductor) transistor comprising a third terminal, a fourth terminal and a gate, the third terminal being connected to the second terminal of the capacitor, the fourth terminal being connected to a connection node of the first and the second inverting amplifier circuits, an inversion signal of the input signal being inputted to the gate.
A transmission circuit comprising a plurality of buffer circuits connected in series,
- wherein each of the buffer circuits comprises:
- a capacitor comprising a first terminal and a second terminal, an input signal being inputted to the first terminal;
- a first inverting amplifier circuit configured to invert and amplify a signal of the second terminal of the capacitor;
- a second inverting amplifier circuit configure to invert and amplify an output signal of the first inverting amplifier circuit;
- and
- a MOS (Metal Oxide Semiconductor) transistor comprising a third terminal, a fourth terminal and a gate, the third terminal being connected to the second terminal of the capacitor, the fourth terminal being connected to a connection node of the first and the second inverting amplifier circuits, an inversion signal of the input signal being inputted to the gate.
A buffer circuit comprising:
- a capacitor comprising a first terminal and a second terminal, an input signal being inputted to the first terminal;
- a first inverting amplifier circuit configured to invert and amplify a signal of the second terminal of the capacitor;
- a second inverting amplifier circuit configure to invert and amplify an output signal of the first inverting amplifier circuit;
- and
- a MOS (Metal Oxide Semiconductor) transistor comprising a third terminal, a fourth terminal and a gate, the third terminal being connected to the second terminal of the capacitor, the fourth terminal being connected to a connection node of the first and the second inverting amplifier circuits, an inversion signal of the input signal being inputted to the gate.
Dependencies are inferred from the claim text.