Universal counter/timer circuit
AssigneeNXP B.V.
InventorsCRAIG A. MACKENNA, NEIL E. BIRNS
Life of this patent
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Abstract
A counter/timer circuit and method of generating timed output signals using the counter/timer circuit, uses multiple counters that are configurable to operate as one or more counters. The counters are controlled by control signals from a control logic circuitry of the counter/timer circuit, where at least some of the control signals are dependent on event signals generated by an event generation module of the counter/timer circuit. The generated event signals are based on at least one of: an input signal, an output signal, and a counter match, qualified by a state value associated with the counters.
Claims20
A counter/timer circuit comprising:
- a counter unit having multiple counters that are configurable to operate as one or more counters;
- an event generation module configured to generate event signals based on at least one predefined event;
- and
- control logic circuitry connected to the counter unit to provide control signals for the counters of the counter unit, the control logic circuitry being also connected to the event generation module to receive the event signals so that at least some of the control signals are dependent on at least some of the event signals.
A method of generating timed output signals using a counter/timer circuit, the method comprising:
- generating event signals based on at least one predefined event;
- providing control signals to counters of the counter/timer circuit, wherein at least some of the control signals are dependent on at least some of the event signals;
- and
- generating count values at the counters using the control signals, the count values representing a unified count value or separate count values depending on the configuration of the counter/timer circuit.
Dependencies are inferred from the claim text.