Wavelet transformation using multicore processors

The method according to claim 1, further comprising:

• classifying a first portion of the wavelet coefficients as low magnitude coefficients and a second portion of the wavelet coefficients as high magnitude coefficients;
• eliminating the common partial products for the high magnitude wavelet coefficients;
• replacing multiplication operations for the low magnitude wavelet coefficients with shift-and-add operations.

The method according to claim 2, further comprising:

• performing the shift-and-add operation employing a shift and add encoding.

The method according to claim 1, further comprising:

• performing the DWT transform by a plurality of processing elements in a multicore processor with each processing element including a high-pass filter element, a low-pass filter element, and a decimation element.

The method according to claim 1, further comprising:

• sorting the wavelet coefficients based on their respective magnitudes;
• and
• computing the wavelet coefficients starting with largest wavelet coefficient.

The method according to claim 6, further comprising:

• applying the DWT based on a partial sum that includes fewer than all wavelet coefficients depending on a predefined error limit.

The method according to claim 1, wherein the set of pixels are associated with one of a still image and a video stream.

The method according to claim 1, further comprising:

• employing five low-pass filter stages, wherein the common partial products are eliminated for first, second, and fifth wavelet coefficients and multiplication operations for third and fourth wavelet coefficients are replaced with shift-and-add operations.

The method according to claim 9, further comprising:

• employing four high-pass filter stages, wherein the common partial products are eliminated for first and fourth wavelet coefficients and multiplication operations for second and third fourth wavelet coefficients are replaced with shift-and-add operations.

The method according to claim 11, further comprising:

• unloading each transformed value in a word-serial manner.

The method according to claim 12, further comprising:

• loading the pixels and unloading the transformed values in a First In First Out (FIFO) manner.

The method according to claim 11, further comprising:

• computing the partial products starting with a largest wavelet coefficient such that the computation converges on a final sum of products.

The method according to claim 11, further comprising:

• employing a plurality of processing elements with four two-stage pipeline inputs each to apply the DWT, wherein one pair of the of the pipelines for each processing element are dedicated to low-pass computations and another pair of the pipelines for each processing element are dedicated to high-pass computations.

The method according to claim 15, wherein one pipeline of each pair of pipelines is fed at the positive edge of a clock signal and another pipeline of each pair of pipelines is fed at the negative edge of the clock signal.

The method according to claim 15, further comprising:

• providing outputs of the plurality of processing elements to a first adder at the positive edge of a clock signal and to a second adder at the negative edge of the clock signal.

The method according to claim 17, further comprising:

• providing transformed values at outputs of the first and second adders to one of a buffer and a Random Access Memory (RAM) for word-serial unloading.

The method according to claim 15, further comprising:

• providing low-pass outputs of the plurality of processing elements to a first adder at the positive edge of a clock signal and to a second adder at the negative edge of the clock signal;
• and
• providing high-pass outputs of the plurality of processing elements to a third adder at the positive edge of a clock signal and to a fourth adder at the negative edge of the clock signal.

The method according to claim 19, wherein the first, second, third, and fourth adders are operated as tree adders.

The IC according to claim 22, wherein the plurality of cores are further adapted to:

• compute the wavelet coefficients starting with largest wavelet coefficient such that the computation converges on a final sum of products.

The IC according to claim 22, further comprising dual RAMs one of which is read out in positive clock edges and the other read out in negative clock edges feeding two independent delay lines one of which is fed in the positive clock edges and the other in the negative clock edges.

The IC according to claim 21, wherein each core further comprises a decimation element.

The IC according to claim 21, wherein the first NOC is a Serial-In-Parallel-Out (SIPO) component.

The IC according to claim 21, wherein the second NOC is a Parallel-In-Serial-Out (PISO) component.

The IC according to claim 21, wherein the processing elements include four two-stage pipeline inputs each with one pair of the of the pipelines for each processing element dedicated to low-pass computations and another pair of the pipelines dedicated to high-pass computations.

The IC according to claim 28, wherein one pipeline of each pair of pipelines is fed at the positive edge of a clock signal and another pipeline of each pair of pipelines is fed at the negative edge of the clock signal.

The IC according to claim 28, wherein outputs of the processing elements are provided to a first adder at the positive edge of a clock signal and to a second adder at the negative edge of the clock signal.

The IC according to claim 30, further comprising one of a buffer and a Random Access Memory (RAM) adapted to receive transformed values from the first and second adders for word-serial unloading.

The IC according to claim 28, wherein low-pass outputs of the processing elements are provided to a first adder at the positive edge of a clock signal and to a second adder at the negative edge of the clock signal, and wherein high-pass outputs of the processing elements are provided to a third adder at the positive edge of a clock signal and to a fourth adder at the negative edge of the clock signal.