Multicast address learning in an input/output adapter of a network processor
AssigneeLSI Corporation
InventorsJoseph A. Manzella, Nilesh S. Vora, Ritchie J. Peachey
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AssigneeLSI Corporation
InventorsJoseph A. Manzella, Nilesh S. Vora, Ritchie J. Peachey
Estimating the term…
An apparatus for supporting multicast address learning in a network processor includes a task parameter decoder receiving the packet and determining parameters of the packet, a plurality of unlearned address counters recording a number of the packets to be multicast, a correlator determining destination addresses of the packet, a multicast replicator replicating the packet multiple times, and a task generator generating a generated packet with a bitmap and sending out the generated packet to an I/O adaptor over a task ring interface of the network processor. If the packet is unlearned, the unlearned address counter is then incremented and the unlearned packet is sent back to a special queue in the I/O adaptor over the task ring interface with an index to the bitmap for replicating by the multicast replicator, after replicating, the unlearned address counter is decremented. Methods for replicating unlearned/learned multicast packets within a network processor are included.
An apparatus for supporting multicast address learning for a packet to be sent to multiple destinations coupled to a network processor, the apparatus comprising:
A multicast replication logic for supporting multicast address learning for a packet to be sent to multiple destinations coupled to a network processor, the multicast replication logic comprising:
A multicast network processor system comprising:
A method for replicating unlearned multicast packets within a network processor comprising:
A method for replicating learned multicast packets within a network processor comprising:
Dependencies are inferred from the claim text.