Hot carrier programming of nand flash memory
AssigneeMacronix International Co., Ltd.
InventorsShaw-Hung Ku, I-Chen Yang
Life of this patent
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Abstract
A NAND memory device includes strings of NAND memory cells, where each memory cell includes a charge trapping structure formed over a lightly-doped substrate region. A selected one of the NAND memory cells can be programmed by application of a relatively low program voltage in combination with a previously-applied set-up voltage, which is applied to the substrate for initiating inversion. The inversion in the substrate causes electrons to become hot in the channel regions, including the channel of the selected memory cell. As a result, the relatively lower program voltage can be used at the control gate of the selected memory cell for sufficiently energizing hot electrons to tunnel into the charge trapping structure of the selected memory cell.
Claims25
A memory comprising:
- a plurality of memory cells arranged in series in a semiconductor body;
- a plurality of word lines, each word line in the plurality of word lines being coupled to a respective one of the plurality of memory cells;
- and
- control circuitry coupled to the plurality of word lines, the control circuitry being adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by:
- biasing one of first and second ends of the plurality of memory cells to a set-up voltage;
- reducing the voltage level being applied to the one of the first and second ends of the plurality of memory cells from the set-up voltage to a bit-line programming voltage;
- applying a pass voltage to word lines corresponding to unselected memory cells;
- and
- applying a program voltage to the selected word line corresponding to the selected memory cell.
A memory comprising:
- a first string of memory cells arranged in series in a semiconductor body;
- a second string of memory cells arranged in series in the semiconductor body;
- a plurality of word lines, each word line in the plurality of word lines being coupled to a respective one of the first string of memory cells and to a respective one of the second string of memory cells;
- and
- control circuitry coupled to the plurality of word lines, the control circuitry being adapted for programming a selected memory cell in the first string of memory cells corresponding to a selected word line by:
- applying a bit-line programming voltage to one of first and second ends of the first string of memory cells;
- maintaining first and second ends of the second string of memory cells at a ground level voltage;
- applying a pass voltage to word lines corresponding to unselected memory cells;
- and
- applying a program voltage to the selected word line corresponding to the selected memory cell.
Dependencies are inferred from the claim text.