Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorJumpei SATO
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Abstract
A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in a shape of a matrix along a plurality of parallel bit lines and a plurality of word lines intersecting orthogonally to the bit lines, and that have their data read out to the bit lines; a sense amplifier which detects a voltage or a current of the bit line and decides the read data from each of the memory cells; a clamping transistor connected between the sense amplifier and the bit lines to determine a voltage in a charging mode of the bit lines by a clamp voltage applied to a gate thereof; and a clamp voltage generation circuit which generates the clamp voltage so as to become larger as a distance from the sense amplifier to a selected one of the memory cells is longer.
Claims11
A semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells that are arranged in a shape of a matrix along a plurality of bit lines arranged in parallel and a plurality of word lines intersecting orthogonally to the bit lines;
- a sense amplifier;
- a clamping transistor connected between the sense amplifier and the bit lines and a clamp voltage applied to a gate thereof;
- and
- a clamp voltage generation circuit generating the clamp voltage;
- wherein the memory cell array is divided into a plurality of blocks in a direction in which the bit lines extend, and m groups (m>2) include two or more the plurality of blocks, and the clamp voltage generation circuit determines the clamp voltage on the basis of said m groups to which the selected memory cell belongs.
Dependencies are inferred from the claim text.