Semiconductor storage device

A semiconductor storage device comprising:

• a memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells each of which is selected by the word line and the bit line, the memory cell array being divided into a plurality of blocks, some of the word lines being set to a specific word line, at least some of or all the memory cells in each block being set to specific memory cells, the memory cell being accessed by the specific word line, the specific data except user data being stored in the specific memory cell;
• and
• an erasing circuit that erases the memory cell of the memory cell array, the erasing circuit having a cycle during which a first voltage is applied to the specific word line belonging to the certain block while a second voltage different from the first voltage is applied to the remaining word lines before an erasing operation during an erasing cycle of the memory cell belonging to the certain block, the erasing cycle including the erasing operation performed to the memory cell and processing necessary for the erasing operation.

A semiconductor storage device comprising:

• a memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells each of which is selected by the word line and the bit line, the memory cell array being divided into a plurality of blocks, some of the word lines being set to a specific word line, at least some of or all the memory cells in each block being set to specific memory cells, the memory cell being accessed by the specific word line, the specific data except user data being stored in the specific memory cell;
• and
• an access circuit that accesses the memory cell of the memory cell array, the access circuit referring to the specific data stored in the specific memory cell belonging to the certain block in performing an access operation to the memory cell belonging to the certain block.