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US 2012/0236629 A1Published application
Multi-level dram cell using chc technology
AssigneeNanya Technology Corporation
InventorWerner Juengling
Life of this patent
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Abstract
A DRAM memory cell includes: a first finFET structure; and a second finFET structure adjacent to the first finFET structure. The second finFET structure includes: a source follower transistor in a first fin of the second finFET structure; an access transistor in a second fin of the second fin FET structure; a write word line; and a read word line stacked above the write word line. When the read word line is fired high, the source follower transistor enables data to be read from the first finFET structure.
Claims6
A DRAM memory cell, comprising:
- a first finFET structure;
- and
- a second finFET structure adjacent to the first finFET structure, the second finFET structure comprising:
- a source follower transistor in a first fin of the second finFET structure;
- an access transistor in a second fin of the second fin FET structure;
- a write word line;
- and
- a read word line stacked above the write word line;
- wherein when the read word line is fired high, the source follower transistor enables data to be read from the first finFET structure.
6 more elements
Dependencies are inferred from the claim text.