Solid state storage device with removable power backup

A solid state storage device comprising:

• a printed circuit board assembly;
• a memory arranged on the printed circuit board assembly;
• a storage medium arranged on the printed circuit board assembly;
• a processor arranged on the printed circuit board assembly, wherein the processor is coupled to the memory and to the storage medium via the printed circuit board assembly, and wherein the processor is configured to store data in the memory and the storage medium and to read data from the memory and the storage medium;
• a plurality of capacitors serially arranged and connected to the printed circuit board assembly to supply backup power to the processor, the memory, and the storage medium;
• and
• a monitor circuit configured to monitor a voltage at a positive plate of each of the plurality of capacitors.

A solid state storage device comprising:

• a printed circuit board assembly;
• a memory arranged on the printed circuit board assembly;
• a storage medium arranged on the printed circuit board assembly;
• a processor arranged on the printed circuit board assembly, wherein the processor is coupled to the memory and to the storage medium via the printed circuit board assembly, and wherein the processor is configured to store data in the memory and the storage medium and to read data from the memory and the storage medium;
• a plurality of capacitors serially arranged and connected to the printed circuit board assembly to supply backup power to the processor, the memory, and the storage medium;
• and
• an active balance network configured to equalize the respective voltages across the plurality of capacitors, wherein the active balance network comprises:
• a first plurality of resistors arranged in a first voltage divider circuit configured to equally divide the total voltage across the plurality of capacitors;
• and
• a plurality of op amps configured as voltage followers,
• wherein the output of each of the plurality of op amps is coupled to a respective terminal connecting two adjacent capacitors, and an input of each of the plurality of op amps is coupled to a respective terminal connecting two adjacent resistors in the first voltage divider circuit.