Systems and Methods for Sync Mark Detection

A method for sync mark detection, the method comprising:

• receiving a series of digital samples embodying a sync mark pattern;
• providing a first sync pattern corresponding to a first phase;
• providing a second sync pattern corresponding to a second phase;
• calculating a difference between the series of digital samples and the first sync pattern to yield a first comparison value corresponding to the first phase;
• calculating a difference between the series of digital samples and the second sync pattern to yield a second comparison value corresponding to the second phase;
• comparing the first comparison value with the second comparison value, wherein the first comparison value is less than the second comparison value;
• and
• providing the first phase as a phase correction output.

A storage device, the storage device comprising:

• a storage medium maintaining information;
• a read/write head assembly operable to sense the information and to provide a corresponding continuous signal;
• an analog front end circuit operable to process the continuous signal to yield an analog input;
• an analog to digital converter circuit operable to sample the analog input synchronous to a sampling clock to yield a set of digital samples;
• a first comparison circuit operable to compare the set of digital samples with a first sync pattern to yield a first comparison value corresponding to a first phase;
• a second comparison circuit operable to compare the set of digital samples with a second sync pattern to yield a second comparison value corresponding to a second phase;
• a comparator circuit operable to identify the first comparison value as less than the second comparison value, and to provide the first phase as a phase correction output;
• and
• a phase correction circuit operable to adjust the sampling clock based at least in part on the phase correction output.