Liquid crystal display device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorHajime KIMURA
Life of this patent
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Abstract
To suppress a malfunction of a circuit due to deterioration in a transistor. In a transistor which continuously outputs signals having certain levels (e.g., L-level signals) in a pixel or a circuit, the direction of current flowing through the transistor is changed (inverted). That is, by changing the level of voltage applied to a first terminal and a second terminal (terminals serving as a source and a drain) every given period, the source and the drain are switched every given period. Specifically, in a portion which successively outputs signals having certain levels (e.g., L-level signals) in a circuit including a transistor, L-level signals having a plurality of different potentials (L-level signals whose potentials are changed every given period) are used as the signals having certain levels.
Claims26
A liquid crystal display device comprising:
- a first transistor;
- a second transistor;
- and
- a third transistor,
- wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, and the other of the source and the drain of the first transistor is electrically connected to a third wiring,
- wherein one of a source and a drain of the second transistor is electrically connected to a second wiring, and the other of the source and the drain of the second transistor is electrically connected to the third wiring,
- wherein a gate of the third transistor is electrically connected to the third wiring,
- wherein the third transistor is turned on by a selection signal and is turned off by a non-selection signal,
- wherein the selection signal is supplied from the first wiring to the third wiring in a period during which the first transistor is on,
- wherein the non-selection signal is supplied from the second wiring to the third wiring in a period during which the second transistor is on, and
- wherein at least one of the selection signal and the non-selection signal is a signal whose potential is changed every predetermined period.
A liquid crystal display device comprising:
- a first transistor;
- a second transistor;
- a third transistor;
- and
- a fourth transistor,
- wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, and the other of the source and the drain of the first transistor is electrically connected to a third wiring,
- wherein one of a source and a drain of the second transistor is electrically connected to a second wiring, and the other of the source and the drain of the second transistor is electrically connected to the third wiring,
- wherein one of a source and a drain of the fourth transistor is electrically connected to the second wiring, and the other of the source and the drain of the fourth transistor is electrically connected to the third wiring,
- wherein a gate of the third transistor is electrically connected to the third wiring,
- wherein the third transistor is turned on by a selection signal and is turned off by a non-selection signal,
- wherein the selection signal is supplied from the first wiring to the third wiring in a period during which the first transistor is on,
- wherein the non-selection signal is supplied from the second wiring to the third wiring in a period during which at least one of the second transistor and the fourth transistor is on, and
- wherein at least one of the selection signal and the non-selection signal is a signal whose potential is changed every predetermined period.
A semiconductor device comprising:
- a first transistor;
- a second transistor whose first terminal is electrically connected to a first terminal of the first transistor;
- a third transistor whose first terminal is electrically connected to the first terminal of the first transistor;
- a fourth transistor whose gate terminal is electrically connected to the first terminal of the first transistor,
- wherein the first terminal of the first transistor is one of source and drain terminals of the first transistor,
- wherein the first terminal of the second transistor is one of source and drain terminals of the second transistor,
- wherein the first terminal of the third transistor is one of source and drain terminals of the third transistor, and
- wherein at least one of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises a semiconductor layer that comprise a channel formation region comprising an oxide semiconductor.
A semiconductor device comprising:
- a first transistor;
- a second transistor whose first terminal is electrically connected to a first terminal of the first transistor;
- a third transistor whose first terminal is electrically connected to the first terminal of the first transistor;
- a fourth transistor whose gate terminal is electrically connected to the first terminal of the first transistor;
- a fifth transistor;
- a sixth transistor whose first terminal is electrically connected to a first terminal of the fifth transistor;
- a seventh transistor whose first terminal is electrically connected to the first terminal of the fifth transistor;
- an eighth transistor whose gate terminal is electrically connected to the first terminal of the fifth transistor;
- a ninth transistor;
- a tenth transistor whose first terminal is electrically connected to a first terminal of the ninth transistor;
- an eleventh transistor whose first terminal is electrically connected to the first terminal of the ninth transistor;
- a twelfth transistor whose gate terminal is electrically connected to the first terminal of the ninth transistor;
- wherein a second terminal of the second transistor, a second terminal of the seventh transistor, and a second terminal of the tenth transistor are electrically connected to one another,
- wherein a second terminal of the third transistor, a second terminal of the sixth transistor, and a second terminal of the eleventh transistor are electrically connected to one another, and
- wherein at least one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor comprises a semiconductor layer that comprise a channel formation region comprising an oxide semiconductor.
Dependencies are inferred from the claim text.