Apparatuses and methods for reducing errors in analog to digital converters

A method of reducing errors in a successive approximation ADC, comprising:

• comparing a common model signal to a compare input to generate a comparator output;
• generating one or more control signals responsive to the comparator output;
• selectively coupling second sides of capacitors of a capacitor array to an analog input signal and one or more input reference signals responsive to the one or more control signals wherein a first side of the capacitor array is operably coupled to an array output;
• and
• limiting the compare input within a predefined range relative to the array output with a voltage limiter operably coupled between the array output and the compare input.

A successive approximation ADC, comprising:

• a comparator including a first input coupled to a first compare input, a second input coupled to a second compare input, and a comparator output;
• control logic configured to generate one or more control signals responsive to the comparator output;
• a first capacitor array having first sides of first capacitors of the first capacitor array operably coupled to a first array output and configured to selectively couple each of second sides of the first capacitors to an analog input signal and one or more input reference signals responsive to the one or more control signals;
• a second capacitor array having first sides of second capacitors of the second capacitor array operably coupled to a second array output and configured to selectively couple each of second sides of the second capacitors to the analog input signal and the one or more input reference signals responsive to the one or more control signals;
• a first voltage limiter operably coupled between the first array output and the first compare input, the first voltage limiter configured to limit a voltage on the first compare input within a first predefined range relative to the first array output;
• and
• a second voltage limiter operably coupled between the second array output and the second compare input, the second voltage limiter configured to limit a voltage on the second compare input within a second predefined range relative to the second array output.

A method of reducing errors in a successive approximation ADC, comprising:

• comparing a first compare input to a second compare input to generate a comparator output;
• generating one or more control signals responsive to the comparator output;
• selectively coupling second sides of first capacitors of a first capacitor array to an analog input signal and one or more input reference signals responsive to the one or more control signals wherein a first side of the first capacitor array is operably coupled to a first array output;
• limiting the first compare input within a first predefined range relative to the first array output with a first voltage limiter operably coupled between the first array output and the first compare input;
• selectively coupling second sides of second capacitors of a second capacitor array to the analog input signal and one or more input reference signals responsive to the one or more control signals wherein a first side of the second capacitor array is operably coupled to a second array output;
• and
• limiting the second compare input within a second predefined range relative to the second array output with a second voltage limiter operably coupled between the second array output and the compare input.