Digital-to-analog converter and circuit
AssigneeRenesas Electronics Corporation
InventorFumihiko KATO
Life of this patent
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Abstract
The selection circuit is supplied with a low-voltage-side power supply voltage from a low-voltage-side power supply, and outputs a voltage that changes in 2m (m is an integer equal to or greater than 2) levels according to m-bit digital data to be input. The level shift circuit generates a voltage by shifting a level of the voltage output from the selection circuit by a predetermined value. The n (n is an integer equal to or greater than 2)-bit digital-to-analog converter is supplied with a high-voltage-side power supply voltage from a high-voltage-side power supply, and outputs an output voltage that changes in 2(m+n) levels by changing the voltage generated by the level shift circuit in 2n levels according to n (n is an integer equal to or greater than 2)-bit digital data to be input.
Claims20
A digital-to-analog converter comprising:
- a selection circuit that is supplied with a low-voltage-side power supply voltage from a low-voltage-side power supply, and outputs a voltage that changes in 2m (m is an integer equal to or greater than 2) levels depending on m-bit digital data to be input;
- a level shift circuit that generates a voltage by shifting a level of the voltage output from the selection circuit by a predetermined value;
- and
- an n (n is an integer equal to or greater than 2)-bit digital-to-analog converter that is supplied with a high-voltage-side power supply voltage from a high-voltage-side power supply, and outputs an output voltage that changes in 2(m+n) levels by changing the voltage generated by the level shift circuit in 2n levels depending on n-bit digital data to be input.
A circuit comprising:
- a selector coupled to a first power line to output a first voltage and a second voltage;
- a digital-to-analog (D/A) converter coupled to a second power line to output an output voltage based on a first reference voltage and a second reference voltage, the second power line having a higher voltage than that of the first power line;
- and
- a level shifter, wherein
- the level shifter comprises:
- a first transistor having a source thereof coupled to the second power line, a gate thereof coupled to a bias voltage and a drain thereof coupled to the first reference voltage;
- a second transistor having a source thereof coupled to the first reference voltage, a gate thereof coupled to the first voltage and a drain thereof;
- a third transistor having a source thereof coupled to the second power line, a gate thereof coupled to the bias voltage and a drain thereof coupled to the second reference voltage;
- and
- a fourth transistor having a source thereof coupled to the second reference voltage, a gate thereof coupled to the second voltage and drain thereof.
Dependencies are inferred from the claim text.