Split gate structure and method of using same

A method comprising:

• (a) providing a one-time programmable array of memory bit cells, each memory bit cell comprising a transistor having a split gate electrode including first and second gate portions, and a fuse element connected to one of a source or drain of the transistor;
• (b) programming the array of memory bit cells by applying a programming voltage to the first gate portion of the transistor of a subset of the memory bit cells, but not to the second gate portions thereof, the programming voltage sufficient to program the fuse elements of the subset of the memory bit cells;
• and
• (c) after completion of step (b), during reading of the array of memory bit cells, applying a reading voltage only to the second gate portion of the transistor of each memory bit cell to be read, and not applying the reading voltage to the first gate portion of the transistor of each memory bit cell to be read.