Device and method for addressing power to a load selected from a plurality of loads
AssigneeKoninklijke Philips Electronics N.V.
InventorALWIN ROGIER MARTIJN VERSCHUEREN
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Abstract
The invention relates to a device and method for addressing power to at least a selected load from a plurality of loads, in particular light sources in solid state lighting applications, such as decorative indoor and outdoor illumination for buildings or cars, by timing a power signal such as to power a selected load when said common timed power signal is switched to said load under control of a delayed clock signal.
Claims13
Electrical circuit for addressing power to at least a selected load (60;
- 65, 65′, 65″) from a plurality of loads, the circuit comprising a plurality of cascaded subcircuits (100;
- 110), each subcircuit for powering one of the loads, each subcircuit comprising:
- a first input terminal (10) for receiving a timed common power signal;
- a delay element (22) for delaying a clock signal received on a second input terminal (20), the delay element for outputting a delayed clock signal on a output terminal (30);
- and
- a switching element (40;
- 45, 45′, 45″) for switching the common timed power signal to the load, the switching under control of the delayed clock signal,
- characterized in that the delay element comprises a LC resonance circuit formed by at least an inductor (25) and a capacitor (35).
Circuit according to any of the preceding claims, further comprising a clock signal generator for generating the clock signal, and a power signal generator for generating the timed common power signal, the power signal generator being arranged for timing the power signal to power a selected load (60;
- 65, 65′, 65″) when the delayed clock signal switches on the switching element (40;
- 45, 45′, 45″) corresponding said selected load.
Circuit according to any of the preceding claims, wherein the switching element (40;
- 45, 45′, 45″) comprises a JFET.
Circuit according to any of the preceding claims, wherein the load (60) comprises at least a LED (65, 65′, 65″).
Circuit according to one of the preceding claims, further comprising means (96) for preventing reflection of the clock signal after a last subcircuit.
Circuit according to any of the preceding claims, wherein the timed common power signal is an essentially rectangular pulse signal.
Circuit according to any of the preceding claims, wherein the clock signal is a sinusoidal signal.
Circuit according to any of the preceding claims, comprising at least a third input terminal (11, 12), for receiving at least a second timed common power signal.
Circuit according to any of the preceding claims, comprising a first switching element (45) for switching a first common timed power signal to a first load (65), the switching of the first switching element under control of the delayed clock signal, the circuit comprising at least a second switching element (45′, 45″) for switching a second common timed power signal to a second load (65′, 65″), the switching of the at least second switching element under control of the delayed clock signal.
Method for addressing power to at least a selected load (60;
- 65, 65′, 65″) from a plurality of loads, in a circuit comprising a plurality of cascaded subcircuits (100;
- 110), each subcircuit for powering one of the loads, the method comprising:
- receiving a timed common power signal;
- receiving a clock signal;
- delaying the clock signal;
- outputting the delayed clock signal;
- and
- under control of the delayed clock signal, switching the common timed power signal to the load,
- characterized in that the clock signal is delayed by a LC resonance circuit formed by at least an inductor (25) and a capacitor (35).
Dependencies are inferred from the claim text.