Semiconductor Package with Embedded Die and Manufacturing Methods Thereof
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorsKay Stephan Essig, Bernd Karl Appelt, Ming Chiang Lee
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Abstract
A semiconductor package includes a conductive base, a die disposed adjacent to an upper surface of the conductive base, a patterned conductive layer, and a dielectric layer encapsulating the die. The dielectric layer defines an opening through which the patterned conductive layer is electrically connected to the upper surface of the conductive base. The conductive base has a lateral surface including a first portion adjacent to the upper surface of the conductive base and a second portion adjacent to a lower surface of the conductive base, where the second portion is sloped inwardly with respect to the lower surface of the conductive base.
Claims20
A semiconductor package, comprising:
- a conductive base having an upper surface, a lower surface, and a lateral surface, the lateral surface including a first portion adjacent to the upper surface of the conductive base and a second portion adjacent to the lower surface of the conductive base, wherein the second portion is sloped inwardly with respect to the lower surface of the conductive base;
- a die disposed adjacent to the upper surface of the conductive base;
- a patterned conductive layer;
- and
- a dielectric material encapsulating the die, wherein the dielectric material defines an opening through which the patterned conductive layer is electrically connected to the upper surface of the conductive base.
A semiconductor package, comprising:
- a conductive base having an upper surface, a lower surface, and a lateral surface including a first portion adjacent to the upper surface of the conductive base, a second portion adjacent to the lower surface of the conductive base, and an apex at a junction between the first portion and the second portion;
- a die disposed adjacent to the upper surface of the conductive base;
- and
- a dielectric material having a substantially vertical lateral surface and substantially encapsulating the first portion;
- wherein the second portion has an angular offset with respect to the substantially vertical lateral surface.
A method of forming a semiconductor package, comprising:
- providing a metal layer having an upper surface and a lower surface;
- forming a first opening extending from the upper surface of the metal layer partially through the metal layer;
- disposing a die adjacent to the upper surface of the metal layer;
- encapsulating the die and at least a portion of the upper surface of the metal layer with a dielectric layer having an upper surface facing away from the die, the dielectric layer substantially filling the first opening;
- forming a second opening in the dielectric layer, the second opening exposing the upper surface of the metal layer;
- forming a patterned conductive layer adjacent to the upper surface of the dielectric layer;
- forming a conductive via extending through the second opening, the conductive via electrically connecting the patterned conductive layer to the metal layer;
- and
- forming a third opening extending from the lower surface of the metal layer partially through the metal layer, the third opening being substantially aligned with the first opening.
Dependencies are inferred from the claim text.