Semiconductor having a high aspect ratio via

An integrated circuit device comprising:

• a first substrate;
• a second substrate bonded to the first substrate;
• and
• a via structure that electrically couples the first substrate to the second substrate, wherein the via structure includes:
• via sidewall surfaces defined by the second substrate, the via sidewall surfaces extending through the second substrate from a top surface of the second substrate to a bottom surface of the second substrate, the bottom surface of the second substrate being bonded to the first substrate, wherein the via sidewall surfaces have a first portion and a second portion;
• a conductive layer disposed in the second substrate between the via sidewall surfaces, the conductive layer extending through the second substrate from the top surface to the bottom surface, wherein the conductive layer is disposed on the first portion of the via sidewall surfaces;
• and
• an oxide layer disposed between the second portion of the via sidewall surfaces and the conductive layer.

An integrated circuit device comprising:

• a CMOS substrate that includes an interconnection structure that includes a conductive interconnect layer disposed in an insulator layer;
• a MEMS substrate having a first surface and a second surface opposite the first surface, the second surface being bonded to the CMOS substrate;
• and
• a via structure disposed in the CMOS substrate and the MEMS substrate, wherein the via structure electrically couples the CMOS substrate and the MEMS substrate, and further wherein the via structure includes:
• a via sidewall surface defined by the MEMS substrate, the via sidewall surface extending through the MEMS substrate from the first surface to the second surface,
• a via sidewall surface defined by the insulator layer,
• a via bottom surface defined by the conductive interconnect layer, wherein the via sidewall surface defined by the insulator layer extends between the via bottom surface and the via sidewall surface defined by the MEMS substrate,
• a conductive layer disposed in the MEMS substrate and the CMOS substrate, the conductive layer extending through the MEMS substrate from the first surface to the conductive interconnect layer, wherein the conductive layer is disposed over the via sidewall surface defined by the MEMS substrate, the via sidewall surface defined by the insulator layer, and the via bottom surface;
• and
• an oxide layer disposed between the conductive layer and a portion of the via sidewall surface defined by the MEMS substrate.