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US 2012/0235250 A1Published application
Semiconductor device and a method of manufacturing the same
AssigneeRenesas Electronics Corporation
InventorsYutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa
Life of this patent
Estimating the term…
Abstract
In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).
Claims6
A semiconductor device including a power MISFET, comprising:
- a semiconductor substrate;
- a gate insulating film of the power MISFET formed over the semiconductor substrate;
- a gate electrode of the power MISFET formed over the gate insulating film;
- a first impurity region of a first conductive type formed in the semiconductor substrate and formed at one side of the gate electrode;
- a second impurity region of the first conductive type formed in the semiconductor substrate and formed at the other side of the gate electrode;
- an channel region of a second conductive type opposite to the first conductive type formed in the semiconductor substrate, formed under the gate electrode and formed between the first and second impurity regions;
- and
- a offset region of the first conductive type formed between the channel region and the first impurity region and having lower impurity concentration than the first impurity region,
- wherein an interlayer insulating film is formed over the semiconductor substrate,
- wherein a first plug is formed in the interlayer insulating film and is connected with the first impurity region,
- wherein a second plug is formed in the interlayer insulating film and is connected with the second impurity region,
- wherein a first wiring is formed over the interlayer insulating film and is connected with the first plug,
- wherein a second wiring is formed over the interlayer insulating film and is connected with the second plug,
- wherein a field plate is formed over the interlayer insulating film and is arranged over the offset region in planar view, and
- wherein the field plate and the second wiring are electrically connected each other and are formed in the same wiring layer.
12 more elements
Dependencies are inferred from the claim text.