Reducing defect rate during deposition of a channel semiconductor alloy into an in situ recessed active region
AssigneeGlobalfoundries Inc.
InventorsStephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
Life of this patent
Estimating the term…
Abstract
When forming sophisticated high-k metal gate electrode structures on the basis of a threshold voltage adjusting semiconductor alloy, a highly efficient in situ process technique may be applied in order to form a recess in dedicated active regions and refilling the recess with a semiconductor alloy. In order to reduce or avoid etch-related irregularities during the recessing of the active regions, the degree of aluminum contamination during the previous processing, in particular during the formation of the trench isolation regions, may be controlled.
Claims20
A method, comprising:
- forming a trench isolation structure in a semiconductor layer of a semiconductor device in a deposition process environment by reducing a potential of aluminum contamination of said semiconductor layer in said deposition process environment, said trench isolation structure laterally delineating an active region in said semiconductor layer;
- removing material of said active region selectively to said trench isolation structure so as to form a recess;
- forming a layer of a semiconductor alloy in said recess;
- and
- forming a gate electrode structure of a transistor on said layer of a semiconductor alloy.
A method, comprising:
- establishing a first process atmosphere in a first process environment by controlling aluminum contamination of said first process atmosphere;
- forming a trench isolation region in a semiconductor layer of a semiconductor device in said first process atmosphere so as to laterally delineate an active region in said semiconductor layer;
- forming a recess in said active region by establishing an etch atmosphere in a second process environment;
- forming a threshold voltage adjusting semiconductor material in said recess by establishing a deposition atmosphere in said second process environment;
- and
- forming a gate electrode structure of a transistor on said threshold voltage adjusting semiconductor material.
A semiconductor device, comprising:
- a trench isolation structure formed in a semiconductor layer, said trench isolation structure having a substantially uniform aluminum concentration profile along a depth of said trench isolation structure;
- an active region formed in said semiconductor layer and laterally delineated by said trench isolation structure so as to define a first length and a width of said active region;
- a threshold voltage adjusting semiconductor alloy formed on said active region and extending along the width of said active region so as to substantially not overlap with said trench isolation structure;
- and
- a gate electrode structure formed on said threshold voltage adjusting semiconductor alloy, said gate electrode structure comprising a high-k dielectric material and a metal-containing electrode material formed above said high-k dielectric material.
Dependencies are inferred from the claim text.