Method of forming a gate pattern and a semiconductor device

A method of forming a gate pattern, the gate pattern including a plurality of gate bars parallel to each other in a first direction, each gate bar being broken up by gaps, the gaps being located in a plurality of stripe zones parallel to each other in a second direction which is substantially perpendicular to the first direction, and there being the gaps adjacent to each other across the gate bars in each stripe zone, wherein the method comprises the following steps:

• providing, on a gate material layer on a substrate, a plurality of stacked structures which are parallel to each other and extend continuously in the first direction, the stacked structure being composed of a hard mask bar and an etching barrier bar thereon;
• forming a second resist layer on the substrate comprising the stacked structures;
• subjecting the second resist layer to a second photolithography process to selectively leave a plurality of second resist regions, respective second resist regions being located between the gaps to be formed adjacent to each other across the gate bars, respectively;
• selectively removing the etching barrier bars in the stacked structures by a second etching process with the second resist regions as a mask;
• forming a third resist layer on the substrate subjected to the second etching process;
• subjecting the third resist layer to a third photolithography process to form a plurality of openings parallel to each other and extending continuously in the second direction;
• forming gaps in the hard mask bars by a third etching process with the third resist layer subjected to the third photolithography process as a mask;
• and
• forming the gate pattern by a fourth etching process with the hard mask bars subjected to the third etching process as a mask.