Circuit and Method for a Three Dimensional Non-Volatile Memory
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorChih Chieh Yeh
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Abstract
An architecture, circuit and method for providing a very dense, producible, non volatile FLASH memory with SONOS cells. SONOS memory cells are formed using a uniformly doped channel region. A FinFET embodiment cell is disclosed. Because the novel SONOS cells do not rely on diffused regions, the cells may be formed into a three dimensional array of cells without diffusion problems. FLASH memory arrays are formed by forming layers of NAND Flash cells in the local interconnect layers of an integrated circuit, with the metal layers forming the global bit line conductors. The three dimensional non-volatile arrays formed of the SONOS cells rely on conventional semiconductor processing. P-channel and n-channel devices may be used to form the SONOS non-volatile cells.
Claims7
A three dimensional array of non-volatile memory storage cells, comprising:
- a substrate;
- one or more memory layers overlying the substrate, each comprising:
- a uniformly doped silicon region having a plurality of spaced apart memory cell regions formed within it, each memory cell region comprising a source region, a drain region and a channel region between the source and drain regions;
- charge trapping storage dielectrics formed over each of the memory cell regions and overlying the channel region;
- conductive gate electrodes formed overlying the charge trapping storage dielectric for each of the memory cell regions;
- and
- a dielectric layer overlying the gate electrodes and separating the respective memory layers in a vertical direction.
Dependencies are inferred from the claim text.