US 2012/0235218 A1Published application

Semiconductor device and method of manufacturing the same

OwnerHiroyuki KUTSUKAKE, Noboru Shibata +2inventors

InventorsHiroyuki KUTSUKAKE, Noboru Shibata, Kazushige Kanda, Masayuki Ichige

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Abstract

According to one embodiment, a device includes a semiconductor substrate, a first region including a first well which is formed in substrate, a second well which is formed in substrate and on first well, and a memory cell which is formed on second well, and a second region including a third well which is formed in substrate, and a first transistor which is formed on third well. The device includes a third region including a second transistor which is formed on semiconductor substrate, and a fourth region including a fourth well which is formed in semiconductor substrate, a fifth well which is formed in substrate and on fourth well, and a third transistor which is formed on fifth well. Bottoms of first well and fourth well are lower than a bottom of third well, and bottom of third well is lower than bottoms of second well and fifth well.

Claims20

Dependent claims

A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;
a first region including a first well of a second conductivity type which is formed in the semiconductor substrate, a second well of the first conductivity type which is formed in the semiconductor substrate and on the first well, and a memory cell transistor which is formed on the second well;
a second region including a third well of the second conductivity type which is formed in the semiconductor substrate, and a first transistor of the first conductivity type which is formed on the third well;
a third region including a second transistor of the second conductivity type which is formed on the semiconductor substrate;
and
a fourth region including a fourth well of the second conductivity type which is formed in the semiconductor substrate, a fifth well of the first conductivity type which is formed in the semiconductor substrate and on the fourth well, and a third transistor of the second conductivity type which is formed on the fifth well,
wherein a position of each of bottom surfaces of the first well and the fourth well is lower than a position of a bottom surface of the third well, and the position of the bottom surface of the third well is lower than a position of each of bottom surfaces of the second well and the fifth well.

4 more elements

A method of manufacturing a semiconductor device including at least a first region, a second region, a third region and a fourth region, the method comprising:

forming a first mask on a semiconductor substrate of a first conductivity type in the second region and the third region;
forming a first well of a second conductivity type in the first region and a second well of the second conductivity type in the fourth region by using the first mask;
forming a third well of the first conductivity type, which is shallower than the first well, in the first region, and a fourth well of the first conductivity type, which is shallower than the second well, in the fourth region, by using the first mask;
forming a second mask on the semiconductor substrate in the first region, the third region and the fourth region;
and
forming a fifth well of the second conductivity type, which is shallower than the first well and is deeper than the third well, in the second region, by using the second mask.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/235,397Filed 18 Sep 2011
Priority: JP 2011-05982117 Mar 2011
Published: 20 Sep 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10B 41/41
Characterised by the peripheral circuit region: of a memory region comprising a cell select transistor, e.g. NAND
H10B 41/49
Simultaneous manufacture of periphery and memory cells: comprising different types of peripheral transistor
H10D 84/0191
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their doped wells
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe