Timing verification support device, method, and program
AssigneeFujitsu Limited
InventorKatsumi IGUCHI
Life of this patent
Estimating the term…
Abstract
A timing verification support device includes: a storage device to store first circuit data of a semiconductor integrated circuit; a search unit to identify, in the first circuit data, a plurality of circuit elements including a designated circuit element designated as a timing verification target and at least one circuit element included in a path traced when performing timing verification at a boundary between the designated circuit element and a portion other than the designated circuit element; and a generation unit to generate second circuit data for the timing verification including circuit data of the plurality of circuit elements.
Claims16
A timing verification support device comprising:
- a storage device to store first circuit data of a semiconductor integrated circuit;
- a search unit to identify, in the first circuit data, a plurality of circuit elements including a designated circuit element designated as a timing verification target and at least one circuit element included in a path traced when performing timing verification at a boundary between the designated circuit element and a portion other than the designated circuit element;
- and
- a generation unit to generate second circuit data for the timing verification including circuit data of the plurality of circuit elements.
A timing verification support device comprising:
- a storage device to store first circuit data of a semiconductor integrated circuit;
- a search unit to identify a first circuit element group between sequential circuits coupled across a boundary between a plurality of functional blocks obtained by dividing the semiconductor integrated circuit in units of functions, and a second circuit element group included in a path supplying a clock to the first circuit element group, the first circuit element group being included in the first circuit data;
- and
- a generation unit to generate second circuit data for timing verification relating to the boundary between the plurality of functional blocks, the second circuit data including circuit data of the first circuit element group or the second circuit element group, and store the second circuit data in the storage device.
A timing verification support method comprising:
- identifying, by a computer, from first circuit data of a semiconductor integrated circuit in a storage device, a plurality of circuit elements including a designated circuit element designated as a timing verification target and at least one circuit element included in a path traced when performing timing verification at a boundary between the designated circuit element and a portion other than the designated circuit element;
- and
- generating second circuit data for the timing verification including circuit data of the plurality of circuit elements.
A timing verification support method comprising:
- identifying, by a computer, a first circuit element group between sequential circuits coupled across a boundary between a plurality of functional blocks obtained by dividing the semiconductor integrated circuit in units of functions, and a second circuit element group included in a path supplying a clock to the first circuit element group, the first circuit element group being included in a first circuit data in a storage device;
- and
- generating second circuit data for timing verification relating to the boundary between the plurality of functional blocks, the second circuit data including circuit data of the first circuit element group or the second circuit element group, and store the second circuit data in the storage device.
Dependencies are inferred from the claim text.