US 2012/0233575 A1Published application

Layout method for integrated circuit including vias

AssigneeFreescale Semiconductor, Inc.

InventorMadhur KASHYAP

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Abstract

A layout method for an integrated circuit including vias connecting stacked metal layers through cuts in intermediate cut layers includes generating interconnection blockage and obstruction statements that define exclusion regions of the metal layers blocked by existing initial interconnections for routing additional interconnections. Shape, size and spacing data are generated for de-selection areas of the exclusion regions in the conductive layers. The de-selection areas are sufficiently far from the boundaries of the exclusion regions that cut spacing rules applied to the initial cuts within the de-selection areas do not block placement of additional cuts outside the exclusion regions of the conductive layers. Only those of the initial cuts within the exclusion regions that lie outside the de-selection areas are selected. Cut blockage and obstruction statements are generated for the selected cuts. A layout view is derived, including routing the additional interconnections in the electrically conductive layers and placing the additional cuts.

Claims12

Dependent claims

A method of layout and production of a semiconductor integrated circuit including vias connecting a plurality of stacked electrically conductive layers through cuts in at least one electrically insulating intermediate layer, the method comprising:

registering previously routed initial interconnections in said electrically conductive layers and previously placed initial cuts for vias connecting thereto through said intermediate layers;
generating interconnection blockage and obstruction statements that define exclusion regions of said conductive layers blocked for routing additional interconnections in said electrically conductive layers;
generating shape, size and spacing data for de-selection areas of said exclusion regions of said conductive layers, wherein said de-selection areas are sufficiently far from the boundaries of said exclusion regions that cut spacing rules applied to said initial cuts within said de-selection areas do not block placement of additional cuts outside said exclusion regions of said conductive layers;
selecting ones of said initial cuts that lie outside said de-selection areas;
generating cut blockage and obstruction statements for the selected cuts outside said de-selection areas;
deriving a layout view, including routing said additional interconnections in said electrically conductive layers and placing said additional cuts connecting thereto;
using said layout view to produce a mask;
and
using said mask to produce said semiconductor integrated circuit.

6 more elements

A non-transitory computer readable medium with a computer program element thereon that is executable by a data processor in a layout method of a semiconductor integrated circuit including vias connecting a plurality of electrically conductive layers through cuts in at least one electrically insulating intermediate layer, the computer program element comprising instructions for:

registering previously routed initial interconnections in said electrically conductive layers and previously placed initial cuts for vias connecting thereto through said intermediate layers;
generating interconnection blockage and obstruction statements that define exclusion regions of said conductive layers blocked for routing additional interconnections in said electrically conductive layers;
generating shape, size and spacing data for de-selection areas of said exclusion regions of said conductive layers, wherein said de-selection areas are sufficiently far from the boundaries of said exclusion regions that cut spacing rules applied to said initial cuts within said de-selection areas do not block placement of additional cuts outside said exclusion regions of said conductive layers;
selecting ones of said initial cuts that lie outside said de-selection areas;
generating cut blockage and obstruction statements for the selected cuts outside said de-selection areas;
and
deriving a layout view for use in producing a mask and said semiconductor integrated circuit, including routing said additional interconnections in said electrically conductive layers and placing said additional cuts connecting thereto.

4 more elements

Dependencies are inferred from the claim text.