Mixed size data processing operation

Apparatus for processing data comprising:

• processing means for performing data processing operations specified by program instructions;
• a plurality of register means for storing data, each of said register means storing a scalar operand;
• and
• decoder means coupled to said processing means for decoding said program instructions to generate control signals for controlling said processing means to perform data processing operations specified by said program instructions;
• wherein
• said decoder means is configured to decode a mixed operand size instruction to generate control signals to control said processing circuitry to perform a mixed size data processing operation having:
• (i) a first input operand of a first operand size stored within a first register means of said plurality of register means as specified by a first register specifying field within said mixed operand size instruction;
• (ii) a second input operand of a second operand size stored within a second register means of said plurality of register means as specified by a second register specifying field within said mixed operand size instruction, said second operand size being less than said first operand size;
• and
• (iii) a third operand of a third operand size;
• and
• said mixed size data processing operation including processing with a same effect as:
• (a) converting said second input operand from said second operand size to said first operand size;
• and
• (b) generating said third operand in dependence upon said first input operand with said first operand size and said second input operand with said first operand size.

A method of processing data using processing circuitry configured to perform data processing operations specified by program instructions, a plurality of registers, each of said registers storing a scalar operand and decoder circuitry coupled to said processing circuitry and configured to decode said program instructions to generate control signals for controlling said processing circuitry to perform data processing operations specified by said program instructions, said method comprising the steps of:

• decoding a mixed operand size instruction to generate control signals to control said processing circuitry to perform a mixed size data processing operation having:
• (i) a first input operand of a first operand size stored within a first register of said plurality of registers as specified by a first register specifying field within said mixed operand size instruction;
• (ii) a second input operand of a second operand size stored within a second register of said plurality of registers as specified by a second register specifying field within said mixed operand size instruction, said second operand size being less than said first operand size;
• and
• (iii) a third operand of a third operand size;
• and
• said mixed size data processing operation including processing with a same effect as:
• (a) converting said second input operand from said second operand size to said first operand size;
• and
• (b) generating said third operand in dependence upon said first input operand with said first operand size and said second input operand with said first operand size.