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US 2012/0233443 A1Published application
Processor to execute shift right merge instructions
AssigneeIntel Corporation
InventorsJulien Sebot, William W. Macy, Eric Debes, Huy V. Nguyen
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Abstract
Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
Claims20
A processor comprising:
- a plurality of registers;
- an instruction decoder to decode a shift right merge instruction indicating a first 32-bit source operand and a second 32-bit source operand, the first 32-bit source operand including a first four 8-bit byte data elements, the second 32-bit source operand including a second four 8-bit byte data elements;
- and
- an execution unit coupled with the instruction decoder and the plurality of registers, the execution unit in response to the shift right merge instruction to:
- shift the second 32-bit source operand right by one byte;
- merge a least significant 8-bit byte data element of the first 32-bit source operand into a most significant byte position of the shifted second 32-bit source operand to generate a result;
- and
- store the result in a 32-bit destination indicated by the shift right merge instruction.
5 more elements
A processor comprising:
- a plurality of registers, wherein the plurality of registers are to store packed data;
- a cache;
- an instruction fetch unit to fetch a shift right merge instruction;
- an instruction decoder to decode the shift right merge instruction, the shift right merge instruction indicating a first 32-bit source operand in a register of the plurality and a second 32-bit source operand in a register of the plurality, the first 32-bit source operand including a first four 8-bit byte data elements, the second 32-bit source operand including a second four 8-bit byte data elements;
- and
- an execution unit coupled with the instruction decoder and the plurality of registers, the execution unit in response to the shift right merge instruction to:
- shift the second 32-bit source operand right by one byte;
- merge a least significant 8-bit byte data element of the first 32-bit source operand into a most significant byte position of a result that also includes, in a least significant portion thereof, three shifted 8-bit byte data elements of the second 32-bit source operand;
- and
- store the result in a 32-bit destination indicated by the shift right merge instruction, wherein the destination is a register of the plurality.
7 more elements
A system comprising:
- a memory;
- a wireless transceiver;
- a keyboard interface;
- and
- a processor coupled with the memory, the wireless transceiver, and the keyboard interface, the processor comprising:
- a plurality of registers;
- an instruction decoder to decode a shift right merge instruction indicating a first 32-bit source operand and a second 32-bit source operand, the first 32-bit source operand including a first four 8-bit byte data elements, the second 32-bit source operand including a second four 8-bit byte data elements;
- and
- an execution unit coupled with the instruction decoder and the plurality of registers, the execution unit in response to the shift right merge instruction to:
- shift the second 32-bit source operand right by one byte;
- merge a least significant 8-bit byte data element of the first 32-bit source operand into a most significant byte position of the shifted second 32-bit source operand to generate a result;
- and
- store the result in a 32-bit destination indicated by the shift right merge instruction, wherein the system comprises a cellular phone.
10 more elements
A method comprising:
- receiving a shift right merge instruction indicating a first 32-bit source operand in a first register and a second 32-bit source operand in a second register, the first 32-bit source operand including a first four 8-bit byte data elements, the second 32-bit source operand including a second four 8-bit byte data elements;
- and
- in response to the shift right merge instruction:
- shifting the second 32-bit source operand right by one byte;
- merging a least significant 8-bit byte data element of the first 32-bit source operand into a most significant byte position of the shifted second 32-bit source operand to generate a result;
- and
- storing the result in a 32-bit destination register indicated by the shift right merge instruction.
4 more elements
Dependencies are inferred from the claim text.