Address generation in a data processing apparatus

The data processing apparatus as claimed in 19, wherein said full address bit-width is different from said second bit-width associated with said frame offset value.

A data processing apparatus comprising:

• processing circuitry for processing data;
• an instruction decoder responsive to program instructions to generate control signals for controlling said processing circuitry to perform said data processing;
• wherein said program instructions comprise a supplementary program instruction having an instruction size, said instruction decoder being responsive to said supplementary program instruction to perform an address calculating operation for calculating a full address result specifying a memory location of an information entity, said supplementary program instruction having an input operand corresponding to a partial address result calculated from a partial offset value and a non-fixed reference address, wherein said supplementary program instruction comprises at least one supplementary offset field encoding a supplementary offset value and wherein said partial offset value and said supplementary offset value together specify a full offset value.

A data processing apparatus comprising:

• processing circuitry for processing data;
• an instruction decoder responsive to program instructions to generate control signals for controlling said processing circuitry to perform said data processing;
• wherein said program instructions comprise an instruction pair comprising an address calculating instruction having an instruction size and at least one supplementary program instruction, said instruction decoder being responsive to said instruction pair to perform an address calculating operation for calculating a full address result specifying a memory location of an information entity relative to a non-fixed reference address, wherein said address calculating instruction encodes a partial offset value within at least one partial offset field of said address calculating instruction and said at least one supplementary instruction comprises at least one supplementary offset field encoding a supplementary offset value such that said partial offset value and said supplementary offset value together specify said full address result when added to said non-fixed reference address and wherein a combined bit-width of said partial offset value and said supplementary offset value is greater than or equal to said instruction size.

A data processing method for performing data processing on a data processing apparatus, said method comprising:

• in response to program instructions, generating control signals for controlling processing circuitry to perform said data processing;
• in response to an address calculating instruction having an instruction size, performing an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction and wherein said partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction.

A data processing method for performing data processing on a data processing apparatus, said method comprising:

• in response to program instructions, generating control signals for controlling processing circuitry to perform said data processing;
• in response to a supplementary program instruction having an instruction size, performing an address calculating operation for calculating a full address result specifying a memory location of an information entity, said supplementary program instruction having an input operand corresponding to a partial address result calculated from a partial offset value and a non-fixed reference address, wherein said supplementary program instruction comprises at least one supplementary offset field encoding a supplementary offset value and wherein said partial offset value and said supplementary offset value together specify a full offset value.

A data processing method for performing data processing on a data processing apparatus, said method comprising:

• in response to program instructions, generating control signals for controlling processing circuitry to perform said data processing;
• in response to an instruction pair comprising an address calculating instruction having an instruction size and at least one supplementary program instruction, performing an address calculating operation for calculating a full address result specifying a memory location of an information entity relative to a non-fixed reference address, wherein said address calculating instruction encodes a partial offset value within at least one partial offset field of said address calculating instruction and said at least one supplementary instruction comprises at least one supplementary offset field encoding a supplementary offset value such that said partial offset value and said supplementary offset value together specify said full address result when added to said non-fixed reference address and wherein a combined bit-width of said partial offset value and said supplementary offset value is greater than or equal to said instruction size.

A data processing apparatus comprising:

• means for processing data;
• means for decoding responsive to program instructions to generate control signals for controlling said means for processing data to perform said data processing;
• wherein said program instructions comprise an address calculating instruction having an instruction size, said instruction decoder being responsive to said address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction and wherein said partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction.

A data processing apparatus comprising:

• means for processing data;
• means for decoding responsive to program instructions to generate control signals for controlling said means for processing data to perform said data processing;
• wherein said program instructions comprise a supplementary program instruction having an instruction size, said instruction decoder being responsive to said supplementary program instruction to perform an address calculating operation for calculating a full address result specifying a memory location of an information entity, said supplementary program instruction having an input operand corresponding to a partial address result calculated from a partial offset value and a non-fixed reference address, wherein said supplementary program instruction comprises at least one supplementary offset field encoding a supplementary offset value and wherein said partial offset value and said supplementary offset value together specify a full offset value.

A data processing apparatus comprising:

• means for processing data;
• means for decoding responsive to program instructions to generate control signals for controlling said means for processing data to perform said data processing;
• wherein said program instructions comprise an instruction pair comprising an address calculating instruction having an instruction size and at least one supplementary program instruction, said instruction decoder being responsive to said instruction pair to perform an address calculating operation for calculating a full address result specifying a memory location of an information entity relative to a non-fixed reference address, wherein said address calculating instruction encodes a partial offset value within at least one partial offset field of said address calculating instruction and said at least one supplementary instruction comprises at least one supplementary offset field encoding a supplementary offset value such that said partial offset value and said supplementary offset value together specify said full address result when added to said non-fixed reference address and wherein a combined bit-width of said partial offset value and said supplementary offset value is greater than or equal to said instruction size.