Systems, devices, memory controllers, and methods for memory initialization
AssigneeMicron Technology, Inc.
InventorTerry M. Grunzke
Life of this patent
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Abstract
Systems, devices, memory controllers, and methods for initializing memory are described. Initializing memory can include configuring memory devices in parallel. The memory devices can receive a shared enable signal. A unique volume address can be assigned to each of the memory devices.
Claims34
A method for initializing memory, comprising:
- configuring a plurality of memory devices in parallel, wherein the plurality of memory devices receive a shared enable signal;
- and
- assigning a unique volume address to each of the plurality of memory devices.
A method for initializing memory, comprising:
- setting a shared enable signal to a particular state, wherein the shared enable signal is coupled to a plurality of memory devices, and wherein the plurality of memory devices are arranged in a linear daisy chain configuration;
- providing a reset command to each of the plurality of memory devices;
- configuring the plurality of memory devices in parallel;
- and
- assigning a unique volume address to each of the plurality of memory devices.
A method of configuring memory devices associated with a shared enable signal, wherein each of the memory devices has a respective chain input and wherein a reset command is provided to each of the memory devices, the method comprising:
- if the memory devices are to be configured in parallel, configuring each of the memory devices responsive to the reset command regardless of a state of the respective chain input;
- if the memory devices are to be configured sequentially, only configuring a respective one of memory devices if it has an active state on the respective chain input responsive to the reset command.
A memory controller, comprising:
- a first interface for coupling the memory controller to a host;
- and
- a second interface for coupling the memory controller to a plurality of memory devices arranged in a linear daisy chain configuration, wherein the memory controller is configured to:
- set a shared enable signal to a particular state, wherein the shared enable signal is coupled to a plurality of memory devices, and wherein the plurality of memory devices are arranged in a linear daisy chain configuration;
- provide a reset command to each of the plurality of memory devices;
- configure the plurality of memory devices in parallel;
- and
- assign a unique volume address to each of the plurality of memory devices.
A memory controller, comprising:
- a first interface for coupling the memory controller to a host;
- and
- a second interface for coupling the memory controller to a plurality of memory devices arranged in a linear daisy chain configuration, wherein the memory controller is configured to:
- selectively configure the plurality of memory devices in sequence or in parallel;
- and
- assign a unique volume address to each of the plurality of memory devices.
A memory system, comprising:
- a plurality of memory devices coupled in a linear daisy chain configuration;
- and
- a memory controller coupled to the plurality of memory devices, wherein the memory controller is configured to:
- provide a shared enable signal to the plurality of memory devices;
- configure the plurality of memory devices in parallel during an initialization of the plurality of memory devices;
- and
- assign a unique volume address to each of the plurality of memory devices during the initialization.
Dependencies are inferred from the claim text.