Efficient Reduction of Read Disturb Errors in NAND FLASH Memory
AssigneeTexas Memory Systems, Inc.
InventorsHolloway H. Frost, Charles J. Camp, Timothy J. Fisher, James A. Fuxa, Lance W. Shelton
Life of this patent
Estimating the term…
Loading patent…
AssigneeTexas Memory Systems, Inc.
InventorsHolloway H. Frost, Charles J. Camp, Timothy J. Fisher, James A. Fuxa, Lance W. Shelton
Estimating the term…
Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.
A method of reducing read-disturb errors in a memory system comprising a FLASH memory space organized into a plurality of blocks, each block comprising a plurality of pages, and each page defining an individually addressable physical memory location, the method comprising the steps of:
A method of inhibiting read disturb errors in a FLASH memory in which memory locations are divided into pages and blocks, with each page corresponding to a specific physical memory location in which a group of bits can be stored, and each block corresponding to a group of pages, the method comprising the steps of:
A flash memory system comprising:
Dependencies are inferred from the claim text.