Cache System and Processing Apparatus
OwnerKumiko NOMURA, Keiko Abe +1inventors
InventorsKumiko NOMURA, Keiko Abe, Shinobu Fujita
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Abstract
According to an embodiment, a cache system includes a volatile cache memory, a nonvolatile cache memory, an address decoder, and an evacuation unit. The nonvolatile cache memory has a capacity equal to the volatile cache memory. The address decoder designates a same line to the volatile cache memory and the nonvolatile cache memory. The evacuation unit stores data which is inputted from the volatile cache memory and outputs the stored data to the volatile cache memory.
Claims16
A cache system, comprising:
- a volatile cache memory;
- a nonvolatile cache memory having a capacity equal to a capacity of the volatile cache memory;
- an address decoder to designate the same line to the volatile cache memory and the nonvolatile cache memory;
- and
- an evacuation unit to store data to be inputted from the volatile cache memory, the evacuation unit to output the stored data inputted from the volatile cache memory to the volatile cache memory.
A processing apparatus, comprising a cache system and a processor element, wherein the cache system includes:
- a volatile cache memory;
- a nonvolatile cache memory having a capacity equal to a capacity of the volatile cache memory;
- an address decoder to designate the same line to the volatile cache memory and the nonvolatile cache memory;
- and
- an evacuation unit to store data to be inputted from the volatile cache memory and output the stored data to the volatile cache memory,
- wherein the processor element performs operation using data inputted from the volatile cache memory to be outputted from the cache system.
Dependencies are inferred from the claim text.